DFT Engineer

<strong>Job Requirements </strong><br><p>At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.</p><p> </p><p><strong>Key Responsibilities</strong></p><p>Define and review DFT specifications: test strategy, coverage goals, scan architecture, compression, boundary scan (JTAG/1500/iJTAG), MBIST/repair, and SSN methodology.</p><ul><li>Architect and implement hierarchical DFT methodology (block to top-level), enabling scalable ATPG and pattern delivery.</li><li>Define and drive automation strategies for DFT flow enabling hierarchical DFT methodologies using Python/TCL maintain and enhance internal DFT methodology.</li><li>Interface with RTL, STA, PD, verification, and ATE/validation teams for seamless DFT integration and pattern rollout.</li><li>Ensure signoff of DFT timing constraints (SDC), IO and clock constraints, and support STA/debug teams in DFT mode timing closure.</li></ul><p>We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.</p><p> </p><p>We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.</p><br><br><strong>Work Experience </strong><br><h3><span style="color: black;">Technical Skills:</span></h3><ul><li><strong>Tools:</strong> Siemens Tessent (Scan, SSN, MBIST, BISTArchitect, IJTAG, Repair, vcs), synopsys SpyGlass DFT and testmax tools.</li><li><strong>Standards:</strong> IEEE 1149.1/1500, IJTAG, 1687.</li><li><strong>DFT Techniques:</strong> Scan, Compression, Boundary Scan, ATPG, SSN, iJTAG, MBIST, Redundancy Repair, Memory BIST architectures.</li><li><strong>Verification:</strong> VCS/VSIM-based DFT RTL and GLS simulations (0-delay and SDF), fault simulation and coverage analysis.</li><li><strong>STA:</strong> DFT SDCs for scan shift, capture, at-speed, MBIST; understanding of timing exceptions and implications of DFT timing paths.</li><li>Strong scripting expertise in <strong>Python, TCL, Perl</strong> for flow and regression automation.</li></ul><h3><span style="color: black;">Preferred:</span></h3><ul><li>Experience in developing or supporting DFT flow scripts and regression automation.</li><li>Exposure to hierarchical DFT pattern generation and reuse at SoC level.</li><li>Knowledge of low power DFT challenges and power-aware ATPG.</li></ul><p> </p><br><br>