SiMa.ai

No-code edge ML platform with MLSoC

Principal Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeSan Jose, CA, USA

About the Job

Requirements

A BS or MS in Electrical Engineering or Computer Science and 12+ years of experience in functional verification of pipeline-based designs, preferably machine learning accelerators, digital signal processors, central processing units, or graphics processing units.
Very good experience with Universal Verification Methodology and SystemVerilog-based verification methodology.
Working experience developing Universal Verification Methodology and SystemVerilog test benches from scratch, including bus functional models, scoreboards, and SystemVerilog Assertions, along with knowledge of debugging and coverage tools.
Knowledge of Advanced Microcontroller Bus Architecture protocols.
Good debugging, coding, and problem-solving skills.

Responsibilities

Independently perform machine learning accelerator verification execution and closure.
Participate in machine learning accelerator architecture, microarchitecture, and feature discussions and reviews.
Define and develop machine learning accelerator test bench components using Universal Verification Methodology and SystemVerilog.
Develop and execute test plans.
Lead code coverage reviews and closure, and develop and close SystemVerilog Assertion functional coverage.
Manage debugging of test and regression failures.
Help the emulation team triage failures.
Work closely with the Architecture, SoC Hardware, and Software teams.

Desired Qualifications

Experience with silicon debugging in a laboratory or board setup.
Knowledge of formal methods and SystemVerilog Assertions.

Description

Job Title: Principal Engineer, AI & ML Design Verification

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2517

Description:

The Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and data processing at block, sub-system and SoC. As well involved in bring-up and debugging on emulators and silicon.

In addition, this job role requires development, enhancement and on-going support and maintenance of MLA Test Bench and Test Cases for SiMa ML IP.

Job Description

As the experienced MLA Design Verification Engineer, you will

Independently perform MLA verification execution and closure.

Participate in MLA architecture, micro-architecture and feature discussions and reviews.
Define and develop MLA test bench components using UVM & System Verilog.
Develop and execute a test plans.
Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure.
Manage debugging of test and regression failures.
Help emulation team with triaging failures.
Work closely with the Architecture, SoC Hardware and Software teams.

Required Background:

BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
Very good experience of UVM and System Verilog based verification methodology is a must.
Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc..) from scratch along with usage know how of debug & coverage tools.
Skill set for silicon debug on the lab/board set-up is a plus.
Good debug, coding and problem solving skills.
Knowledge of AMBA protocols is a must.
Formal/SVA knowledge is a plus.

Personal attributes:

Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $203,800 - $315,900. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Compensation: 203800 to 315900 (USD) (Annually)

About the Company

SiMa.ai

No-code edge ML platform with MLSoC

SiMa.ai provides a no-code, drag-and-drop environment for building, training, and deploying machine learning models on edge devices. Its platform lets users visually assemble ML solutions without writing code, and runs on its own MLSoC silicon designed for edge computing to reduce latency and speed up inference close to data sources. The product works by combining the no-code development tools with specialized edge-ready hardware, enabling deployment of ML applications such as computer vision on edge devices. SiMa.ai differentiates itself from competitors by pairing a purpose-built MLSoC with an integrated no-code development platform, plus an ecosystem of a developer portal, expert consulting, and a partner program to accelerate AI innovations at the edge. The company aims to broaden access to edge ML, helping individuals and organizations deploy efficient AI at the edge across various industries.

Company size: 201-500
Company stage: Series C
Total funding: $495M
Headquarters: San Jose, CA
Founded: 2018

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