CScale

Optical interconnects for large-scale AI infrastructure

DFT Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

Two years of experience in scan implementation, verification, and debug.
Hands-on experience in scan stitching, pattern generation, and simulation.
Working knowledge of the Siemens Tessent flow for RTL design-for-test insertion and automatic test pattern generation.
Experience in JTAG and scan verification at RTL and gate-level simulation.

Responsibilities

Implement scan architecture and perform scan insertion and stitching at RTL and gate level using the Siemens Tessent flow.
Generate automatic test pattern generation patterns for stuck-at and transition faults and achieve the target test coverage.
Run pattern simulation and debug failures, including mismatches in zero-delay and timing-annotated simulations.
Verify JTAG (TAP controller, instructions, and test data registers) and scan modes at RTL and gate-level simulation.
Run design rule checks for design-for-test and resolve violations with the design team.
Work with the RTL, physical design, and verification teams to close design-for-test requirements and meet timing for scan and test modes.
Support design-for-test signoff checks and release test patterns for tape-out.
Document the design-for-test architecture, test modes, and verification results.

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity.Lasers will fail. Compute shouldn’t.The ambition is simple:Build AI interconnect you can take for granted.CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

Role and Responsibilities

Implement scan architecture and perform scan insertion and stitching at RTL and gate level, using the Siemens Tessent flow.
Generate ATPG patterns (stuck-at, transition) and achieve the target test coverage.
Run pattern simulation and debug failures, including mismatches in zero-delay and timing-annotated simulations.
Verify JTAG (TAP controller, instructions and test data registers) and scan modes at RTL and gate-level simulation (GLS).
Run DFT rule checks (DRC) and resolve violations with the design team.
Work with the RTL, physical design and verification teams to close DFT requirements and meet timing for scan and test modes.
Support DFT signoff checks and release of test patterns for tape-out.
Document the DFT architecture, test modes and verification results.

Requirements

2 years of experience in scan implementation, verification and debug
Hands-on experience in scan stitching, pattern generation and simulation
Working knowledge of the Siemens Tessent flow for RTL DFT insertion and ATPG
Experience in JTAG and scan verification at RTL and GLS

About the Company

CScale

Optical interconnects for large-scale AI infrastructure

CScale builds optical interconnects for large-scale AI computing. Its integrated light engines power gigawatt-scale AI facilities by containing optical failures and keeping compute running across thousands of closely connected accelerators. The hardware provides high-bandwidth, ultra-low-latency optical links to connect accelerators across racks, making data movement between chips dependable for continuous AI workloads. Unlike many data-center components that rely on electronic signaling, CScale focuses on silicon photonics and photonic hardware to deliver scalable, reliable communication at scale. Founded in 2023 in Palo Alto, the company exited stealth in 2026 and has investors including NVIDIA and Intel Capital. Its goal is to enable uninterrupted AI training and inference across large AI infrastructure by delivering dependable optical interconnects that scale as data-center needs grow.

Company size: 51-200
Company stage: Series C
Total funding: $145M
Headquarters: Palo Alto, CA
Founded: 2023

Recently Posted Jobs

Explore more opportunities at CScale

See more jobs