Velaura

Designs energy-efficient AI silicon and systems

Accelerator Compiler and Tool Chain Lead

Systems Software EngineeringConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USA$200k - $300k /yr

About the Job

Requirements

Deep experience with compiler development, machine-learning graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
Strong understanding of machine-learning model formats, graph intermediate representations, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.
Strong C++ and Python programming skills and experience building production-quality compiler or systems software.
Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and software quality assurance.
Experience leading technical teams or major architecture areas.

Responsibilities

Lead architecture and development of the AI accelerator compiler stack.
Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.
Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
Partner with hardware architecture and NPU firmware teams on instruction set architecture, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
Establish compiler verification and regression strategy for graph transformations, intermediate-representation lowering, numerical behavior, model accuracy, and performance.
Hire, mentor, and lead a team of compiler and machine-learning systems engineers.

Desired Qualifications

Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA, TorchDynamo/TorchInductor, or other model import flows.
Familiarity with robotics, computer vision, convolutional neural networks, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
Experience building customer-facing compiler diagnostics and model-porting tools.
Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
Open-source compiler contributions or experience working with external framework communities.

Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)

Role Overview

We are looking for an Accelerator Compiler Lead to own the compiler and model-lowering stack for Velaura’s AI accelerator.This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization integration, code generation, graph partitioning, and compiler diagnostics. The ideal candidate has built or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or other heterogeneous compute targets.

Responsibilities

● Lead architecture and development of the AI accelerator compiler stack.

● Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.

● Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.

● Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.

● Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.

● Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.

● Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.

● Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.

● Establish compiler verification and regression strategy for graph transformations,IR lowering, numerical behavior, model accuracy, and performance.

● Hire, mentor, and lead a team of compiler and ML systems engineers.

Required Qualifications

● Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.

● Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.

● Strong C++ and Python programming skills and experience building production-quality compiler or systems software.

● Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.

● Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.

● Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.

● Experience leading technical teams or major architecture areas.

Preferred Qualifications

● Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.

● Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.

● Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA,TorchDynamo/TorchInductor, or other model import flows.

● Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.

● Experience building customer-facing compiler diagnostics and model-porting tools.

● Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.

● Open-source compiler contributions or experience working with external framework communities.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

About the Company

Velaura

Designs energy-efficient AI silicon and systems

Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.

Company size: 51-200
Company stage: Series A
Total funding: $424M
Headquarters: Santa Clara, CA
Founded: 2022

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