RosaicLabs

Custom x86 chips using Atom RTL

AI Accelerator Design Verification Engineer Intern

Hardware Validation & TestingConfirmed live in the last 24 hours

Internship$30 - $55 /hr

About the Job

Requirements

Working toward a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Recently completed coursework in digital design and verification, covering at least one of computer microarchitecture; digital logic and register-transfer-level design; or constrained-random and coverage-driven verification.
Familiarity with verifying accelerator designs, such as parallel datapaths and single instruction, multiple data (SIMD), single instruction, multiple threads (SIMT), or vector processing; numerical formats and computer arithmetic; and data movement over direct memory access (DMA) and memory interfaces.
Hands-on SystemVerilog experience, including testbench development; Universal Verification Methodology (UVM) is preferred, as are assertions and functional coverage.
Understanding of the end-to-end application-specific integrated circuit (ASIC) design flow and general very-large-scale integration (VLSI) concepts.
Scripting experience in Python, Perl, or Tcl for regression automation.

Responsibilities

Work with a mentor to develop verification plans for the accelerator.
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for the assigned block.
Build tests, scoreboards, and reference models, and close functional and code coverage.
Triage and root-cause failures with RTL designers, with mentorship from senior engineers.
Participate in design and verification reviews and document the verification environment and results.

Desired Qualifications

UVM testbench development experience.
C/C++ experience.

Salary Range: 30 to 55 (Currency: USD) (Pay period: per-hour-wage)

Join our hardware team as an intern or co-op verifying the accelerator, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

What you'll do

Work with your mentor to develop verification plans for the accelerator
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
Build tests, scoreboards, and reference models, and close functional and code coverage
Triage and root-cause failures with RTL designers, with mentorship from senior engineers
Participate in design and verification reviews and document your verification environment and results

Requirements

Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
Familiarity with verifying accelerator designs, such as: parallel datapaths and SIMD / SIMT / vector processing; numerical formats and computer arithmetic; data movement over DMA and memory interfaces
Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
Understanding of the end-to-end ASIC design flow and general VLSI concepts
Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

About the Company

RosaicLabs

Custom x86 chips using Atom RTL

RosaicLabs designs customized processors by licensing Intel’s Atom technology, including RTL, and integrating an Intel x86 core into its own chip designs. The company, based in Santa Clara, operates in stealth mode and aims to build specialized SoCs for targeted workloads, especially in edge and mobile scenarios where energy efficiency matters. The business model hinges on a strategic agreement with Intel that grants access to core IP and RTL, enabling Rosaic to tailor chips for specific applications rather than using off-the-shelf processors. This arrangement also serves as a potential pathway for Intel to monetize its x86 IP and attract new customers for its foundry services. Rosaic’s goal is to create custom silicon platforms that leverage the established x86 software ecosystem while delivering low-power, efficient computing at the edge.

Company size: 1-10
Company stage: Not listed
Total funding: Not listed
Headquarters: Not listed
Founded: Not listed

Recently Posted Jobs

Explore more opportunities at RosaicLabs

See more jobs