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Micron Technology

Makes memory and storage chips for AI and PCs

Principal Advanced CMOS Device & Process Integration Engineer

Hardware EngineeringConfirmed live in the last 24 hours
Full-timeHiroshima, JapanNo salary listedIn-person

About the Job

Requirements

  • A Master of Science or PhD in Electrical Engineering, Electronic Engineering, Semiconductor Engineering, Applied Physics, Materials Science, or a related field, or equivalent experience demonstrating exceptional technical achievement.
  • Extensive industry experience in advanced CMOS device technology, process integration, transistor development, or related semiconductor technology.
  • Expert-level understanding of CMOS transistor physics, process integration, electrical characterization, variability, reliability, and manufacturability.
  • Demonstrated success leading complex technology development or pathfinding programs.
  • Ability to solve highly ambiguous, multidisciplinary technical problems.
  • Ability to influence technical direction across multiple organizations and leadership levels.
  • A strong record of measurable improvements in performance, power, area, reliability, yield, process margin, development cycle time, or manufacturing cost.
  • Technical communication and executive presentation skills.
  • Ability to develop and mentor senior technical talent.

Responsibilities

  • Define the technical strategy and long-term roadmap for advanced CMOS devices and process integration.
  • Establish device architecture, process integration, performance, power, area, reliability, yield, and cost targets for future technology generations.
  • Drive major technical decisions involving device architecture, process complexity, circuit requirements, design rules, manufacturability, and cost.
  • Lead the resolution of complex transistor performance, variability, reliability, yield, and process integration challenges.
  • Create comprehensive silicon learning strategies and ensure experimental plans address critical technology assumptions and risks.
  • Guide electrical test structure strategy, parametric test methodology, process control monitor architecture, and model validation requirements.
  • Establish correlation strategies across silicon measurements, physical analysis, TCAD, compact models, circuit simulation, yield, and product performance.
  • Provide technical leadership for Design Technology Co-Optimization and System Technology Co-Optimization activities.
  • Influence circuit architecture, layout methodology, process design kits, and manufacturing control strategies.
  • Lead technical risk assessments and recommend technology selection, qualification, transfer, and high-volume manufacturing.
  • Serve as a senior technical interface across global development, design, manufacturing, supplier, and research organizations.
  • Develop new technical methodologies, intellectual property, and differentiated device or integration solutions.
  • Represent the organization in executive reviews, technical councils, external collaborations, conferences, and industry forums, as appropriate.
  • Mentor senior engineers, technical leads, and future subject-matter experts.
  • Establish best practices for engineering rigor, data interpretation, technical documentation, and decision-making.
  • Define and scale AI-assisted engineering strategies for data analytics, coding, knowledge retrieval, experiment optimization, predictive modeling, anomaly detection, and technical decision support.
  • Establish validation methods to ensure AI-generated outputs are technically accurate, reproducible, explainable, secure, and appropriate for semiconductor development.
  • Identify opportunities where AI and automation can shorten development cycles, improve learning efficiency, reduce repetitive work, and increase organizational knowledge retention.
  • Maintain final technical accountability for decisions supported by AI-assisted analyses.

Desired Qualifications

  • Recognized expertise in future CMOS device architectures.
  • Experience leading advanced CMOS technology from pathfinding through qualification and high-volume manufacturing.
  • Deep understanding of DRAM peripheral CMOS requirements and the interaction between memory architecture, circuit design, CMOS technology, and manufacturing.
  • Extensive experience with TCAD, compact modeling, SPICE model validation, DTCO, STCO, or technology benchmarking.
  • Experience defining advanced test structures, process control strategies, and electrical characterization methodologies.
  • A track record of patents, publications, major technical innovations, or industry-recognized contributions.
  • Experience building scalable engineering analytics, automation, AI, or machine-learning methodologies.
  • Experience working with global research organizations, equipment suppliers, foundry partners, or academic institutions.
  • Ability to communicate complex technical trade-offs clearly to engineering, executive, and business audiences.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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