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Rambus

Licenses high-speed chip-to-chip connectivity IP

CAD Engineer Intern

Silicon & ASIC DesignPosted on Nov 10
InternshipSan Jose, CA, USA

About the Job

Requirements

  • Currently pursuing a Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Understand digital logic design, RTL, and ASIC/SoC design fundamentals.
  • Have familiarity with digital implementation methodology, such as logic synthesis, static timing analysis, or power analysis.
  • Have programming or scripting experience in Python, Tcl, Bash, or similar languages.
  • Be familiar with Linux environments and software development fundamentals, including debugging and version control.
  • Have creative, analytical, debugging, and problem-solving skills, and be able to work independently and collaborate across teams.
  • Be interested in applying automation and emerging AI technologies to engineering problems.
  • Be willing to take the lead on work, decisions, actions, and consequences.

Responsibilities

  • Develop, maintain, and enhance CAD methodologies and automation flows supporting digital ASIC design, verification, and implementation.
  • Work with industry-standard EDA tools across formal verification, synthesis, static timing analysis (STA), and power analysis to improve design quality, productivity, and flow efficiency.
  • Develop Python-, Tcl-, and shell-based scripts and utilities to automate design workflows, analyze results, and streamline engineering processes.
  • Explore and develop AI-assisted solutions for practical challenges in CAD and semiconductor design workflows, including engineering data analysis, debugging, and workflow investigation.
  • Investigate and deploy applications of large language models (LLMs), retrieval-augmented generation (RAG), and AI agents for engineering automation and intelligent workflow assistance.
  • Build and integrate AI-enabled utilities with existing engineering tools and workflows, assessing their accuracy, reliability, performance, and practical effectiveness.
  • Collaborate with cross-functional CAD, design, verification, and physical design teams to understand engineering challenges, translate requirements into technical solutions, and validate solutions.
  • Gain exposure to broader physical design and signoff methodologies, including place and route (P&R), physical verification (DRC/LVS), and related implementation flows.

Desired Qualifications

  • Have hands-on experience with standard EDA tools from Synopsys, Cadence, or Siemens.
  • Understand timing constraints, timing closure, power optimization, and power, performance, and area (PPA) tradeoffs.
  • Have exposure to place and route (P&R), formal verification, physical verification (DRC/LVS), or related signoff methodologies.
  • Have experience with AI/ML technologies, including LLMs, RAG, AI agents, or agentic automation.
  • Understand what to build and how to build it, rather than relying entirely on AI tools.
  • Have experience developing Python-based tools, MCPs, APIs, or automation frameworks.
  • Have up-to-date knowledge of AI tools.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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