Senior ASIC Design Engineer

About Positron AI

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Chips built for the training era keep running into two walls at inference time: memory bandwidth and chip-to-chip networking. We designed our architecture to break through both. Our first-generation Atlas systems are deploying in Oracle Cloud Infrastructure. Asimov, our first custom ASIC, takes that architecture to silicon. In simulations, Asimov delivers several times more tokens per dollar and tokens per watt than leading GPUs, at a fraction of the power. Paired in our Titan system, Asimov is built to serve models beyond 16 trillion parameters. In September 2026, we raised $875 million at a $5 billion valuation. NEA led the round, joined by Atreides Management, Valor Equity Partners, and others, to bring Asimov and Titan to market. Our team includes engineers from Groq, Lambda, NVIDIA, Meta, F5, and many other industry leaders.

Role Overview

As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency.

Key Responsibilities

Microarchitecture & RTL Leadership:

• Define and document microarchitecture for complex IP blocks/subsystems.
• Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions.

Technical Ownership & Signoff:

• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.

Advanced Interface & Memory Integration:

• Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR).
• Engage with IP vendors and internal stakeholders to ensure seamless integration.

Methodology & Best Practices:

• Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
• Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency.

Cross-Functional Collaboration:

• Partner closely with Verification to define test plans and reference models.
• Work with Architecture and Performance teams to correlate models against RTL.
• Support bring-up, post-silicon debug, and customer engagements as required.

Mentorship & Technical Leadership:

• Guide junior engineers in design techniques, methodology, and problem-solving.
• Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions.

Required Qualifications

• BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
• Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes.
• Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
• Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites.
• Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths.
• Strong cross-functional communication skills, capable of leading technical discussions and producing clear specifications.

Preferred Qualifications

• Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning).
• Formal verification/SVA expertise for property checking and design assertions.
• Experience with low-power design techniques (clock-/power-gating, UPF/CPF).
• Collaboration experience with cocotb/UVM for checkers and reference model co-development.
• Familiarity with RISC-V subsystems, coherence protocols, or customer-owned tooling (COT) flows.

Leveling & Scope

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

Why Join Us?

• Shape the next generation of AI inference hardware with a high-caliber, collaborative team.
• Take technical ownership of critical silicon components that directly impact product success.
• Competitive salary + equity, comprehensive benefits, and flexible work environment.
• Opportunities to innovate, lead, and grow your influence in a rapidly evolving space.

Compensation and Benefits

The base salary range for this role is $200,000 – $300,000.

Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.

Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.