K

Kepler

Ultra-low-voltage computing hardware and memory

Principal Engineer - DFT

Hardware Validation & TestingUpdated on Oct 29
Full-timeSan Jose, CA, USA$250k - $310k /yrIn-person

About the Job

Requirements

  • A B.Tech, M.Tech, or MS in Electrical Engineering, ECE, Computer Engineering, or a related field is required.
  • At least 15 years of hands-on DFT architecture and implementation experience on complex ASIC/SoC designs, including multiple silicon tapeouts, is required.
  • Deep ATPG expertise in stuck-at, transition, path delay, and cell-aware testing using industry-standard DFT tools is required.
  • Strong MBIST architecture and implementation experience on large designs is required.
  • Hands-on experience designing or modifying programmable BIST engines for memory testing, including repair flow and diagnostics, is required.
  • Strong knowledge of JTAG TAP controller design and boundary scan, including BSR, BSDL, and compliance, is required.
  • A solid understanding of hierarchical DFT architecture, scan chain partitioning, and scan compression is required.
  • An understanding of DFT-aware RTL practices and DFT interaction with physical design is required.
  • Experience with ATE interfaces and production test program development is required.
  • Strong scripting skills in Python, Tcl, and Perl are required.

Responsibilities

  • Own DFT architecture and implementation end to end, from definition through RTL, netlist, verification, and tapeout.
  • Drive the design of programmable memory BIST engines, including test algorithms, address sequencing, repair flow, and fail analysis tailored to the memory architecture.
  • Design repair and redundancy management, including hard and soft repair and repair data storage, as well as fail logging and diagnostics infrastructure.
  • Define DFT strategy for full-scan ATPG, embedded compression, MBIST, JTAG, boundary scan, and hierarchical test integration.
  • Drive test coverage closure, including fault models, coverage targets, and ATPG pattern optimization.
  • Work with architecture, RTL, physical design, packaging, and post-silicon validation teams to build DFT-aware decisions early.
  • Set DFT best practices, sign-off infrastructure, and documentation standards.

Desired Qualifications

  • Experience with memory test, repair, and yield learning in high-volume manufacturing is preferred.
  • Knowledge of DFT and test strategies for 3D innovations is preferred.
  • Prior startup experience with lean teams and aggressive schedules is preferred.

About the Company

Kepler

Ultra-low-voltage computing hardware and memory

Kepler Computing, Inc. develops energy-efficient computing hardware with an ultra-low voltage architecture for memory and logic. Its products include 3D stacked compute and memory units, majority logic gates using input paraelectric capacitors, low-power sequential circuits, and memory bit-cells based on non-linear polar materials. The design uses multi-node, heterogeneous technologies to boost computational power while lowering energy consumption, aiming to outperform traditional silicon-based solutions. Kepler differentiates itself by integrating novel materials (ferroelectric/non-linear polar materials), paraelectric capacitor-based logic, and 3D stacked memory in compact, low-power blocks rather than relying on conventional silicon scaling. Its goal is to deliver more powerful computing hardware that consumes less energy, enabling high-performance computing with significantly improved energy efficiency.

Company size
51-200
Company stage
Grant
Total funding
$734M
Headquarters
Berkeley, CA
Founded
2018

Recently Posted Jobs

Explore more opportunities at Kepler

See more jobs