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CTG

IT services integration and digital branding

PDK Testsite Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeRemote in USA$72 - $74 /hrRemote

About the Job

Requirements

  • Proficiency with Cadence Virtuoso or similar integrated circuit design and physical layout tools.
  • Understanding of semiconductor devices, fabrication processes, physical layout, and technology characterization.
  • Knowledge of semiconductor design rules, Design Rule Checking (DRC), Layout Versus Schematic (LVS), and physical verification methodologies.
  • Ability to translate technology specifications and characterization requirements into functional test structures.
  • Strong analytical, troubleshooting, debugging, and problem-solving skills.
  • Ability to interpret electrical measurement results and support silicon-level analysis.
  • Experience with Process Design Kit (PDK) development, validation, or related semiconductor design enablement activities.
  • Strong technical documentation and cross-functional communication skills.
  • Experience developing semiconductor test structures, testsites, test chips, physical layouts, or PDK components.
  • Experience using Cadence Virtuoso or comparable integrated circuit design and layout tools.
  • Experience with semiconductor design rule implementation and physical verification.
  • Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group.
  • A bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Physics, or a related technical discipline, or equivalent relevant experience.

Responsibilities

  • Design and develop semiconductor testsites, test chips, and device-level structures for process technology characterization and Process Design Kit (PDK) development.
  • Create and modify physical layouts using Cadence Virtuoso or comparable electronic design automation (EDA) tools.
  • Translate process characterization and device modeling requirements into test structures and silicon-ready layouts.
  • Interpret semiconductor design rules, technology ground rules, and layout specifications.
  • Perform and debug physical verification, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
  • Support testsite development through design, verification, tapeout preparation, and silicon characterization.
  • Analyze electrical measurement and silicon test results to identify device, interconnect, process, and design issues.
  • Support the development and validation of PDK components, including device definitions, parameterized cells (PCells), technology files, models, and verification flows.
  • Develop and maintain scripts to automate testsite generation, layout, verification, and data-processing workflows.
  • Troubleshoot layout, PDK, physical verification, and EDA tool issues.
  • Document testsite designs, verification methodologies, results, and engineering findings.
  • Collaborate with process development, device modeling, design enablement, layout, CAD/EDA, test, and manufacturing teams.

Desired Qualifications

  • Experience with Cadence SKILL programming, Python, Tcl, or similar scripting languages.
  • Experience developing PCells, layout automation, or verification workflows.
  • Familiarity with Synopsys IC Validator (ICV), Siemens Calibre, or comparable physical verification tools.
  • Experience with PDK development and validation, advanced semiconductor technology nodes, device characterization, or electrical measurement techniques.
  • Experience supporting test structures or test chips through design verification and tapeout.

About the Company

CTG

IT services integration and digital branding

CTG Belgium is integrating with the Cegeka family to combine IT services and digital branding. The teams collaborate closely to align capabilities and deliver more value to clients, especially in digital channels and branding. They are phasing out the CTG Belgium channel and directing followers to Cegeka’s channels, signaling a unified brand presence. Their work centers on blending Cegeka’s and CTG’s expertise to provide coordinated IT services and digital solutions for customers. The main goal is a smooth brand transition and a stronger, shared offering powered by Cegeka and CTG together.

Company size
201-500
Company stage
IPO
Headquarters
Buffalo, NY
Founded
1966

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