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Micron Technology

Makes memory and storage chips for AI and PCs

HBM SoC Physical Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeRichardson, TX, USANo salary listedIn-person

About the Job

Requirements

  • Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
  • Proficiency with industry electronic design automation tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, and Siemens Calibre or equivalent.
  • Understanding of static timing analysis fundamentals, clocking, constraints using Synopsys Design Constraints, and closure techniques including buffering, path shaping, and useful skew.
  • Experience with power intent and power delivery considerations, including Unified Power Format or Common Power Format concepts, power grid planning, and power-gating implications.
  • Familiarity with physical verification and signoff concepts, including design-rule checking, layout-versus-schematic, electrical-rule checking, parasitic-extraction awareness, and signoff handoff quality.

Responsibilities

  • Own physical implementation for SoC blocks or top-level designs, including floor-planning, placement, clock-tree synthesis, routing, and physical optimization to meet performance, power, and area targets.
  • Drive setup and hold timing closure across multi-mode, multi-corner scenarios and partner with RTL, architecture, and static-timing-analysis/signoff teams to converge designs.
  • Integrate and implement complex intellectual property, including controllers, microcontrollers, network-on-chip, interfaces, memory built-in self-test or design-for-test logic, buffers, and PHY-adjacent logic, with focus on physical integration and timing and power integrity.
  • Perform or coordinate physical signoff, including design-rule checking, layout-versus-schematic, infrared drop and electromigration, and timing signoff, and address violations efficiently.
  • Partner with design-for-test teams to ensure scan and memory built-in self-test requirements are physically realizable without compromising performance, power, area, or schedule.
  • Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
  • Support tape-out execution through checklists, engineering-change-order flows, and signoff reviews, and contribute to post-silicon debug by correlating silicon behavior with physical-design, static-timing-analysis, and power analysis.
  • Identify flow gaps and improve productivity through scripting, automation, and best-practice methodology development.

Desired Qualifications

  • Experience with HBM or DRAM-adjacent SoC designs, or memory-subsystem-heavy SoCs.
  • A bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
  • At least 10 years of experience in a related field.
  • Ability to mentor and develop engineers early in their careers.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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