Senior Technical Program Manager-CPU Cores

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THE ROLE

We are seeking a highly skilled Senior Technical Program Manager to drive the adoption of AI-driven methodologies and tooling across our x86 Core Development Organization. This role spans the full pre-silicon lifecycle, including functional verification, RTL design, and physical design, and offers the opportunity to help transform how next-generation AMD x86 CPUs are developed.

You will turn promising AI/ML approaches into scalable, repeatable programs that improve engineering efficiency and design quality. Rather than building isolated point solutions, you will help shape how AI is integrated into day-to-day core development workflows across the organization.

You will define program goals, manage schedules and risks, and coordinate dependencies across design, verification, physical design, architecture, and data engineering teams. Partnering closely with the Cores leadership team, you will align priorities, track measurable efficiency and quality gains, and influence the broader AI adoption strategy for the organization.

This role provides direct exposure to Cores leadership and the opportunity to collaborate with industry-leading engineers developing next-generation AMD x86 CPUs. It requires strong technical fluency in CPU core development flows and AI/ML methods, exceptional program management capabilities, and the ability to influence strategy and priorities at the leadership level.

THE PERSON

The ideal candidate combines technical credibility across CPU core development, including functional verification, RTL design, and/or physical design, with a working knowledge of AI/ML techniques and how they can be applied to engineering workflows.

You are comfortable going deep into design and verification flows, model approaches, and tooling architecture while also establishing clarity, ownership, and predictable delivery across teams that may be new to AI-driven ways of working. You can translate complex technical opportunities into structured programs, align stakeholders across organizations, and drive measurable outcomes.

You are motivated by the opportunity to lead meaningful transformation, work with cutting-edge technologies and resources, and contribute to a culture focused on continuous innovation. You want to influence how AI changes engineering work at scale while helping teams deliver higher-quality designs more efficiently.

KEY RESPONSIBILITIES:

• Drive the definition and deployment of AI-enabled program strategies across verification, RTL design, and physical design within x86 core development.

• Identify and prioritize opportunities to apply machine learning, data analytics, and automation to engineering workflows (e.g., predictive coverage modeling, test/testbench generation, timing and congestion prediction, floorplan and place-and-route optimization, RTL code assistance, anomaly detection in regression and bring-up data, root-cause and failure triage).

• Develop program plans, define milestones, manage inter-team dependencies, and maintain program KPIs tied to verification velocity, coverage closure, PPA (power, performance, area) targets, and design-cycle schedule adherence.

• Coordinate cross-functional work across architecture, RTL/design, verification, DFT, physical design, performance modeling, and internal tooling/data engineering teams to build and scale intelligent workflows.

• Partner with EDA and internal tooling teams to define the infrastructure, data pipelines, and compute requirements needed to collect, clean, and analyze large volumes of simulation, coverage, timing, and layout data in support of AI/ML initiatives.

• Evaluate emerging AI tools and solutions (open-source, EDA-vendor, and internally built) for applicability across the core development lifecycle, and drive build-vs-buy recommendations.

• Identify, track, and mitigate program risks and issues; escalate when needed and drive corrective action with stakeholders.

• Facilitate effective communication and alignment across design, verification, and physical design teams, as well as with EDA partners and tool vendors; serve as primary program point-of-contact for AI adoption initiatives.

• Track and report measurable improvements in engineering efficiency and design quality — including verification velocity, coverage efficiency, bug/defect escape rate, and design-cycle throughput — resulting from AI-driven methods.

• Mentor and coordinate with engineering leads and other program managers to scale successful AI adoption pilots into repeatable, organization-wide practices.

• Support technical tradeoffs and prioritization discussions by preparing data-backed analyses, schedules, and impact assessments for engineering and executive leadership.

• Proactively identify risks, execution gaps, and systemic bottlenecks in the adoption of new methodologies; implement mitigation plans and hold teams accountable to closure.

• Facilitate stakeholder communication and present technical progress, risks, and tradeoffs to leadership with clarity.

PREFERRED EXPERIENCE:

• Significant experience in CPU or SoC development, with hands-on background in one or more of: functional verification, RTL design, or physical design/implementation.

• Proven TPM or technical program leadership delivering complex, cross-functional programs end-to-end in ambiguous, fast-changing environments.

• Working knowledge of AI/ML or data science techniques and demonstrated experience applying them (or overseeing their application) to hardware design, verification, or EDA-related problems.

• Solid understanding of core development flows and tooling (e.g., simulation, regression, coverage collection and debug for verification; RTL/synthesis flows for design; timing, place-and-route, and physical verification for physical design), sufficient to credibly scope and prioritize AI initiatives across these domains.

• Demonstrated experience with program planning tools (Jira, Confluence, MS Project, or equivalent) and agile delivery practices.

• Excellent stakeholder management, written and verbal communication, and presentation skills; comfortable engaging at both engineering and executive levels.

• Direct hands-on experience with Python and common ML frameworks/tooling (e.g., TensorFlow, PyTorch, Scikit-learn) as applied to engineering or EDA data.

• Experience working with large datasets, relational databases, and visualization tools (e.g., Pandas, SQL, Tableau) in a silicon design or verification context.

• Prior experience developing or deploying ML models for EDA, verification, or physical design applications specifically.

• Familiarity with model training/monitoring tools (e.g., TensorBoard, MLflow, Weights & Biases) and reinforcement learning or active learning approaches in constrained engineering domains.

• Experience spanning more than one of verification, RTL design, and physical design, or experience leading programs that cut across multiple core-development disciplines.

ACADEMIC CREDENTIALS:

• A master's or bachelor's degree in computer engineering, Computer Science, or Electrical Engineering is desired.

LOCATION: 

Fishkill, NY is preferred, open to other AMD locations

THIS ROLE IS NOT ELIGIBLE FOR VISA SPONSORSHIP

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.