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Why is Intel stock surging? AUO deal, AI chip plans and 18A progress explained. Intel stock is surging in pre-market trading. Intel shares jumped 5.9% in pre-open trading on Monday, extending the strong rally seen last week. The stock had recently broken out of its trading range, adding to the upward momentum. A new Intel-AUO partnership is the main reason behind the latest jump. Intel has reportedly partnered with AUO Optronics, a major Taiwanese display-panel maker, to develop Micro LED advanced packaging technology.

Intel begins High-NA EUV production; stitching remains a key challenge. 2026-09-21 10:40:35 Intel Foundry has officially put ASML's High-NA EUV lithography into commercial production, but technical challenges around stitching larger chip designs are still in development ahead of full high-volume manufacturing. The technology has been used on over one million wafers across tool certification, R&D and production runs, including select layers of the Intel Core Ultra Series 3 processors codenamed Panther Lake processor. Intel reports overlay, throughput and tool availability are hitting targets, with Intel 18A process layers patterned with High-NA delivering equivalent yield, defect rates, electrical performance and reliability as layers made with conventional 0.33-NA EUV. The Panther Lake trial did not prove the industry has solved the most difficult stitching challenges, however. The High-NA patterned layers were intentionally selected so no electrical connections needed to cross the boundary between the two half-fields. The test was designed solely to prove High-NA can operate in a real production flow and build manufacturing experience, without altering the performance of the final product. This distinction is important, as the core optical design of High-NA creates an inherent field-size limitation. Why EUV stitching technology is required for next-gen chips. Conventional 0.33-NA EUV tools use standard 6x6-inch masks to expose a 26 mm x 33 mm field. High-NA increases numerical aperture to 0.55 for far better resolution, but its anamorphic optics cut the exposure field in half, to just 26 mm x 16.5 mm. Small designs fit easily inside this half-field, but larger chip designs require either two stitched exposures, or eventually, a larger mask. This challenge is growing more urgent as advanced chips get larger. "The need for stitching has only grown," Chris Mack, co-founder and CTO of lithography metrology software firm Fractilia, shared in a recent interview. AI accelerators and other large chips are increasingly filling the full conventional reticle field, he explained, making full-field High-NA patterning a high priority for the industry. Intel Foundry is pursuing multiple solutions to address this gap. The simplest approach, used for Panther Lake, is to avoid any electrically significant crossings at the seam entirely. A more flexible option is block-and-route stitching, where designers place the seam so critical standard-cell circuitry does not cross it, and route connections through higher metal layers instead. Mark Phillips, distinguished engineer at Intel Foundry, describes block-and-route as one step in a broader strategy for using existing 6-inch masks with High-NA. Intel is also developing two-dimensional "Zipzag" stitching, where the seam can move around sensitive circuitry or IP blocks instead of running in a straight line. The name refers to the zigzag stitch used in sewing. Rather than forcing the boundary between two High-NA exposures to run straight across the die, Zipzag lets the seam jog around sensitive design regions. This gives chip designers more freedom to keep critical circuitry away from the stitching boundary, though it also adds complexity to mask construction, inspection and manufacturing control. Electrical validation of stitching methods is rolling out in phases. Intel has already successfully electrically verified block-and-route on a full-loop test chip with a straight-line seam. Test structures compare the resistance and variation of metal lines crossing the stitching boundary with control structures that do not cross it, while additional chain and comb designs check for shorts and open connections. The latest Zipzag test chip goes a step further, with electrical test structures spanning a jogged seam. Inline imaging, overlay and defect measurements show the jogged regions are performing as expected, but full electrical test results are still pending. Mack notes block-and-route is a relatively low-risk approach. "It seems relatively straightforward, it seems low risk, and it looks like that is the path that everyone will try for their first stitching exercises," he said. The far more challenging use case is feature stitching, where critical features themselves cross the boundary between two exposures. This requires far tighter control over how the two patterns align and overlap. "What we're talking about is making the technology ready for high-volume semiconductor manufacturing," Mack said. At that scale, the problem goes beyond just overlay alignment: dose, focus, edge placement and stochastic variation all impact final performance. Stitching processes must hold up against rare statistical failures. Relevant stitching errors can be as small as a few nanometers, while stochastic edge roughness in the lithography process is also on the nanometer scale. Manufacturers therefore need to clearly distinguish systematic errors caused by stitching from random variation that is already inherent to the lithography process. Metrology tools add another layer of challenge. Scanning electron microscopes, the standard tool for measuring these tiny features, introduce image noise that can look identical to real stochastic variation on the wafer. Fractilia is working with Intel on methods to separate these effects and accurately measure systematic stitching errors. Average performance results alone are not enough to validate a stitching process, Mack adds. Rare failures in the long tails of statistical distributions can appear at parts-per-million or even parts-per-billion levels. A stitching process that looks healthy on average can still cause significant yield issues once millions of devices are being manufactured. That is why yield is the ultimate measure of success, far more important than a clean one-off demonstration. "Yield is the big unknown until you actually run the experiments," Mack said. This same uncertainty complicates cost comparisons between High-NA and continued multi-patterning with 0.33-NA EUV. Engineers can model the cost of one High-NA exposure against two, three, or four lower-NA exposures, but the calculation can shift drastically if one approach delivers significantly better yield. Intel's Panther Lake trial was not designed to demonstrate an economic advantage for High-NA. The High-NA step replaced a 0.33-NA step in the production flow with no change to the final product, focused entirely on proving production readiness and learning how the tools perform under real manufacturing loads. Larger 6x12-inch masks could eliminate stitching needs long-term. Stitching may not be a permanent requirement. Intel and ASML are leading industry efforts to adopt larger 6x12-inch masks. A mask twice as large in one dimension would allow a High-NA scanner to expose a full conventional reticle field without any stitching required. Intel notes the larger format could also improve productivity on 0.33-NA EUV tools by combining processes that would otherwise require two separate 6-inch masks. Mack says he is confident stitching will work for near-term use cases, but sees larger masks as the preferable long-term solution. "The productivity improvements that come from using a 6x12 mask alone will justify its use," he said. The transition to larger masks will not happen quickly. Based on discussions at the SPIE Photomask Technology + Extreme Ultraviolet Lithography conference in Monterey in early September, Mack says the industry is aligning around the larger mask roadmap, with first mask demonstrations expected in roughly five years, and production-ready masks for wafer printing expected seven years from now. This timeline means stitching will play a critical role in advanced chip manufacturing for years to come. Intel has already demonstrated that High-NA itself can operate reliably in production. The next challenge is making stitching sufficiently predictable, measurable, and easy to design around so that customers can use the smaller High-NA field without compromising yield. The core optical technology is already deployed in fabs around the world. The harder remaining task is making all supporting processes routine for high-volume production.

AU Optronics and Intel could reshape chip packaging, merging Micro LED displays with silicon & CPOs to chase AI demands. Intel is rapidly working on its advanced packaging capabilities, now reportedly partnering with AU Optronics for CPO & massively integrated chips. AU Optronics & Intel are combining their advanced packaging capabilities to fuel the era of CPO (Co-Packaged Optics) & beyond. The future demands a vast acceleration in the field of advanced packaging to sidestep the slowdown of Moore's Law. Advanced Packaging solutions are a necessity in the modern world as AI and compute demands swell intensively. Given this demand, Intel is reportedly planning to join hands with Taiwanese Optoelectronics giant AU Optronics, or AUO. As a part of this collaboration, Intel will fully enter the field of Micro LED substrates, a specialty of the Taiwanese manufacturer (AUO). This will allow Intel and AUO to jointly develop CPO and high-density chip layouts with advanced integrated solutions. As per United Daily News, Intel declined to comment on the reports but AUO's chairman has previously said that the company has entered into advanced packaging and glass substrates. Intel's experience with glass substrates and advanced packaging solutions such as EMIB makes sense for AUO to join them in this race. Intel is also said to have recently obtained a U.S. patent which involves the packaging of ICs on Micro LED substrates. The patent discusses the embedding of portions of the semiconductor chip within a glass substrate containing TGVs (Through-Glass-Vias) as opposed to TSVs (Through-Silicon-Vias). Intel is making a push for advanced packaging, and in addition to developing its Embedded Multi-Chip Interconnect Bridge (EMIB) series of technologies, it has recently entered the field of advanced packaging for Micro LED substrates. It is reported that Intel has partnered with AU Optronics, the Taiwanese company with the most extensive experience in Micro LED, to jointly develop CPO and high-density computing chip integration solutions. Machine Translated via UDN This research is said to offer a heterogeneous optoelectronic integration solution which is ideal for CPO (Co-Packaged Optics) and highly-dense compute packages. On the other hand, AU Optronics currently has a solid ecosystem built around Micro LED CPOs, Glass Substrates, RDL and optical Interconnect. Industry experts state that this overlaps with Intel's own progress in the field, hence both companies coming together will be beneficial for the industry as a whole. Intel's reported outreach to AU Optronics underscores a clear strategic shift: pairing its EMIB packaging push and glass-substrate ambitions with AUO's deep Micro LED, TGV, and RDL expertise. The overlap, especially around co-packaged optics and heterogeneous integration of chips with in-substrate Micro LEDs, positions both companies to chase next-generation high-density computing and optical interconnect demand. While neither side has confirmed the alliance, the technical fit and AUO's existing partner work on glass substrates and CPO make the collaboration a logical, and potentially high-impact, next step in Intel's advanced packaging race. About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking. Follow Wccftech on Google to get more of its news coverage in your feeds.