Technical Leader DFT & STA

<p><b>Meet the team</b></p><p></p><p>Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions.</p><p></p><p></p><p><b>Your Impact</b></p><p></p><p>You are a detail-oriented DFT Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity.</p><p>You will collaborate effectively with cross-functional teams, communicate complex timing data clearly.</p><p></p><p></p><p><b>Responsibilities will include:</b></p><ul><li>Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.</li><li>Check timing for unconstrained endpoints, no clock, etc.</li><li>Your role may include SDC validation, CDC delay check, and SDC flow development.</li><li>Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.</li></ul><p></p><p></p><p><b>Minimum Qualifications</b></p><ul><li>Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.</li><li>Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes).</li><li>Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime.</li><li>Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages.</li></ul><p></p><p></p><p><b>Preferred Qualifications</b></p><ul><li>Master’s degree in electrical or computer engineering (or other equivalent field) with 6+ years of related work experience.</li><li>Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.</li><li>Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime.</li><li>Prior working experience with synthesis tools: Synopsys Fusion Compiler.</li><li>Prior working experience with Tessent tool: DFT insertion in RTL.</li><li>Strong communication skills and team player.</li></ul><p></p><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><p></p>