ASIC DFT Engineer

<p style="color:!important"><span style="color:#525252"><span><b>Meet The Team:</b></span></span></p><br /><p style="color:!important"><span style="color:#525252"><span>The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With 2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. </span></span></p><br /><p style="color:!important"><span style="color:#525252"><span><b>Your Impact:</b></span></span></p><br /><p style="color:!important"><span style="color:#525252"><span>• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.  </span></span></p><br /><p style="color:!important"><span style="color:#525252"><span>You are an ASIC Design for Test Hardware Engineer with 4-8 years of related work experience with a broad mix of technologies. </span></span></p><br /><p style="color:!important"><span style="color:#525252"><span><b>Minimum Qualifications: </b></span></span></p><br /><p style="color:!important"><span style="color:#525252"><span>• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least <b>4-8 years of experience</b>. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Knowledge of the latest innovative trends in DFT, test and silicon engineering. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Experience with Jtag protocols, Scan insertion and ATPG, BScan</span></span></p><p style="color:!important"><span style="color:#525252"><span>• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets.</span></span></p><p style="color:!important"><span style="color:#525252"><span>• Knowledge of the latest innovative trends in DFT, test and silicon engineering.</span></span></p><p style="color:!important"><span style="color:#525252"><span>• Experience working with Gate level simulation, debugging with VCS and other simulators. </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Strong verbal skills and ability to thrive in a multifaceted environment </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Scripting skills: Tcl, Python/Perl. </span></span></p><br /><p style="color:!important"><span style="color:#525252"><span><b>Preferred Qualifications: </b></span></span></p><br /><p style="color:!important"><span style="color:#525252"><span>• Test Static Timing Analysis </span></span></p><p style="color:!important"><span style="color:#525252"><span>• Post silicon validation using DFT patterns. </span></span></p><p style="color:!important"><span style="color:#000000"> </span></p><br /><h1>Why Cisco? </h1><p>At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.</p><p>Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. </p><p>We are Cisco, and our power starts with you. </p><br /><p><b><u>Disclaimer</u></b></p><p>To ensure that we hire the best talent in the right way, we follow a strict hiring process and recently, Cisco has been made aware of fraudulent recruiters claiming to be from the company. Please be advised that any communication from Cisco about careers will:</p><ul><li>be in direct response to an application you have submitted through the company career site</li><li>begin with screening or an interview</li><li>originate from a Cisco email address, and</li><li>be conducted across email, phone, or WebEx</li></ul><p> </p><p>Cisco will never make a job offer without conducting an interview process or ask you for money in any way. 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