FPGA Design Engineer - Avionics

Salary Range: 150000 to 250000 (Currency: USD) (Pay period: per-year-salary)

Key Responsibilities:

• Design and implement RTL in SystemVerilog or VHDL for satellite avionics FPGAs across a variety of FPGA platforms.
• Develop AXI Memory-Mapped and AXI-Stream protocol implementations for inter-subsystem communication.
• Perform FPGA resource and size estimation including logic, memory, and DSP budgeting.
• Implement clock-domain-crossing (CDC) design techniques and verify timing closure across designs.
• Design clock/reset tree architectures and manage timing-closure strategies for complex multi-clock designs.
• Develop SPI, I²C, GPIO, and other low-speed peripheral interfaces alongside high-speed transceiver links.
• Apply fault-tolerant digital design techniques including TMR, ECC, scrubbing, and SEE mitigation.
• Perform synthesis and place-and-route using vendor toolchains, including custom placement constraints.
• Support board bring-up by developing configuration, interface verification, and debug test sequences.
• Collaborate with digital design, power, and PCB layout engineers to ensure FPGA support circuitry meets requirements.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of FPGA design experience in aerospace, defense, or high-reliability systems.
• Proficiency in SystemVerilog and/or VHDL for RTL design.
• Experience with FPGA synthesis, place-and-route, and timing closure workflows.
• Demonstrated knowledge of AXI or similar bus protocols and interface design.
• Experience with clock-domain crossing techniques, FIFO design, and multi-clock architectures.
• Understanding of radiation effects on FPGAs and mitigation strategies (TMR, ECC, scrubbing).

Preferred Qualifications:

• Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based, anti-fuse architectures).
• Background in signal processing (FFT, FIR/IIR filters) and DSP integration.
• Experience with transceiver design and high-speed serial communications on FPGAs.
• Exposure to DAC/ADC interfaces and mixed-signal digital handling.
• Experience with satellite or spacecraft FPGA applications.
• Proficiency in Python or TCL scripting for automation and build infrastructure.

Tools & Technologies:

• FPGA vendor toolchains (synthesis, place-and-route, timing analysis)
• RTL simulation tools (e.g., VCS, QuestaSim, or equivalent)
• Python, TCL, or shell scripting for build automation
• Makefiles for FPGA build workflows

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.