Hardware Signal/Power Integrity Engineer
FuriosaAI
Hardware Signal/Power Integrity Engineer
FuriosaAI
Power-efficient AI inference accelerator chips
FuriosaAI builds high-performance, high-efficiency AI compute for the Inference Era. Founded in 2017 by veteran semiconductor and AI algorithm engineers, Furiosa operates globally with offices in Korea and Silicon Valley, along with a compiler-focused R&D lab in Lisbon.
Our vision is to make AI computing sustainable, enabling access to powerful AI for everyone on Earth. We solve the AI hardware energy and operational cost crisis at the architectural level, rather than through brute force, building the world's first truly AI-native compute platform to unlock the full potential of artificial intelligence for every enterprise.
Define SI/PI requirements based on IP and system-level specifications.
Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
Develop SI/PI methodologies for advanced packaging technologies such as chiplet, 3D-IC, D2D (die-to-die), and C2C (chip-to-chip) interfaces.
Cover SI/PI analysis and optimization at the full system level, including on-chip, package, and PCB domains.
Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
Collaborate with silicon, package, and board teams to ensure accurate measurement-simulation correlation and system-level robustness.
Support debug and bring-up efforts in the lab when needed.
Work with internal teams and partners to co-optimize SI/PI solutions.
BS or MS in Electrical Engineering, Physics, or a related field.
8+ years of experience in component- and system-level SI/PI analysis.
Solid understanding of SI/PI fundamentals and methodologies.
Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.
PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
Candidates with one or more of the following experiences will be given strong consideration:
SI/PI analysis and optimization for high-speed digital systems and standard interfaces (e.g., PCIe, DDR, Ethernet)
Model and analyze complex 3D structures using EM simulation tools
On-chip Backend sign-off (Static/Dynamic IR, EM)
On-/Off-chip PDN modeling and budgeting
On-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating
Early-stage reference clock jitter estimation and sign-off methodology development
Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
The defining bottleneck of the AI era is building the right hardware and software stack to run it at global scale. Furiosa is solving this challenge holistically from the ground up.
With our flagship chip, RNGD, in mass production today and our next-generation platform in development with Broadcom, we are proving that full-stack, tensor-native compute is the future of AI infrastructure. This is a pivotal moment to join our team, right as we accelerate our global expansion.
At Furiosa, you will:
Solve AI’s Most Urgent Challenge. Help build the high-performance, energy-efficient inference hardware and software required to fulfill the promise of advanced AI.
Pioneer Full-Stack Co-Design. Work with teams that are architecting solutions from silicon up through the compiler (featuring innovations like Tensor Contraction Language and Virtual ISA) and serving frameworks.
Ship Real-World Silicon, Software, and Solutions. Turn breakthrough technology into commercial deployment. RNGD is in mass production with TSMC and running live enterprise workloads for global leaders like LG AI Research and Samsung SDS.
Partner With the Industry's Best. Collaborate across an elite global ecosystem that includes TSMC, Broadcom, SK Hynix, and GUC.
Do Your Life’s Best Work. Join a brilliant, low-ego, mission-driven team in a high-trust environment that values autonomy, intellectual curiosity, and shared ambition.
FuriosaAI develops AI accelerators for data centers. Its flagship RNGD chip is a power-efficient accelerator designed to boost performance per watt for running large language models and other demanding AI workloads. The hardware is configurable with multiple processing elements to fit different workloads, and it is paired with advanced compiler technology and profiling tools to identify bottlenecks and optimize efficiency. This combination of flexible hardware and software optimization differentiates FuriosaAI from competitors, focusing on maximizing performance while keeping energy use low. The company targets data centers and enterprises that need high-performance, energy-efficient AI solutions, and aims to make AI computing more sustainable and scalable by selling its chips and related software tools and pursuing long-term contracts with large-scale customers.
Explore more opportunities at FuriosaAI