Velaura

Designs energy-efficient AI silicon and systems

Design Verification Engineer CPU

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeSanta Clara, CA, USA$200k - $300k /yr

About the Job

Requirements

At least 8 years of experience verifying high-performance CPUs or complex digital designs.
Strong computer architecture and microarchitecture fundamentals.
Experience with SystemVerilog, Universal Verification Methodology (UVM), C, C++, assertions, and coverage-driven verification.
Experience independently owning a design block or unit from test planning through coverage closure.
Experience writing test plans, portable testbenches, and transactors.
Experience debugging complex issues across hardware and software boundaries.
A Bachelor of Science degree or higher in Computer Engineering, Electrical Engineering, or Computer Science.
Ability to work effectively in a collaborative multidisciplinary engineering environment.

Responsibilities

Own verification of custom CPU units, including instruction fetch, decode, load/store, and instruction, data, and last-level caches.
Work with CPU and SoC architects to understand the intent behind a new microarchitecture and create detailed test and coverage plans.
Build verification environments using SystemVerilog, UVM, C, and C++, including stimulus, checkers, assertions, trackers, and coverage that are portable across block and subsystem environments.
Develop instruction-level stimulus and compare it against a golden instruction set simulator.
Verify memory ordering, coherence, exceptions, and privilege behavior against the architecture specification.
Verify latency, bandwidth, and cache behavior against high-performance targets under representative workloads.
Run regressions during design and environment bring-up, and track progress using bug and coverage metrics.
Support emulation, FPGA prototyping, and pre-silicon software bring-up, and drive root-cause analysis across hardware and software boundaries.

Desired Qualifications

Knowledge of the ARM or RISC-V instruction set architecture.
Knowledge of microprocessor verification domains such as cache coherence, memory ordering, prefetching, branch prediction, speculative execution, and address translation.
Prior experience verifying front-end, fetch, load/store, instruction cache, data cache, or last-level cache units.
Knowledge of vector units or matrix multiplication units.
Experience with random instruction sequencing, formal verification, gate-level simulation, or silicon bring-up.
Experience verifying a custom processor developed from scratch rather than an integrated third-party core.
Experience leading a small team of verification engineers.
Experience using AI-assisted verification workflows to improve productivity and coverage.

Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)

Role Overview

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.

This role focuses on our custom CPU. We are designing a leading edge, high performance processor from scratch, and you will own a functional domain of its verification from test plan through coverage closure, proving that a newly designed microarchitecture behaves as intended.

Responsibilities

Own verification of custom CPU units including instruction fetch, decode, load store, and the instruction, data and last level caches.

Work with CPU and SoC architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans.

Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.

Develop instruction level stimulus and compare against a golden instruction set simulator.

Verify memory ordering, coherence, exceptions and privilege behavior against the architecture specification.

Verify latency, bandwidth and cache behavior against high performance targets under representative workloads.

Execute regressions through design and environment bring up, and track progress using bug and coverage metrics.

Support emulation, FPGA prototyping and pre silicon software bring up, and drive root cause analysis across hardware and software boundaries.

Required Qualifications

8 or more years verifying high performance CPUs or complex digital designs.

Strong computer architecture and microarchitecture fundamentals.

Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.

Experience owning a block or unit of a design independently from test plan through coverage closure.

Experience writing test plans, portable testbenches and transactors.

Experience debugging complex issues across hardware and software boundaries.

BS or higher in Computer Engineering, Electrical Engineering or Computer Science.

Ability to work effectively in a collaborative multidisciplinary engineering environment.

Preferred Qualifications

Knowledge of the ARM or RISC-V instruction set architecture.

Knowledge of microprocessor verification domains such as cache coherence, memory ordering, prefetching, branch prediction, speculative execution and address translation.

Prior experience verifying front end, fetch, load store, instruction cache, data cache or last level cache units.

Knowledge of vector units or matrix multiplication units.

Experience with random instruction sequencing, formal verification, gate level simulation or silicon bring up.

Experience verifying a custom processor developed from scratch rather than an integrated third party core.

Experience leading a small team of verification engineers.

Experience using AI assisted verification workflows to improve productivity and coverage.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

About the Company

Velaura

Designs energy-efficient AI silicon and systems

Velaura AI designs and manufactures ultra-energy-efficient AI infrastructure, including 3nm ASIC chips, Teraflux mining systems, FluxVision fleet-management software, and AuraLinks rack-level networking. Customers deploy the hardware in data centers, while FluxVision monitors and manages fleets; EnergyTune and AutoTune dynamically adjust power to meet grid stability, and AuraLinks reduces bottlenecks in AI training and inference. The company differentiates itself with a team of silicon architects from Apple, Google, and Qualcomm, plus a patent-pending energy-management approach and a fully integrated hardware-software stack. Its goal is to enable massive AI deployment by delivering powerful, energy-efficient compute and networking that aligns with sustainable energy grids and domestically produced technology.

Company size: 51-200
Company stage: Series A
Total funding: $424M
Headquarters: Santa Clara, CA
Founded: 2022

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