Staff Signal Integrity Engineer

• Lead end-to-end signal integrity definition, channel budgeting, and stackup optimization for complex multi-die packages, including 2.5D (CoWoS, EMIB, InFO), 3D vertical stacking, and high-density organic substrates.
• Architect and optimize multi-terabit interconnects across Die-to-Die (UCIe/BoW), host links (PCIe Gen6/7, PAM4/# SerDes), and memory subsystems (HBM3/4, DDR5, LPDDR6) in close collaboration with PHY and silicon design teams.
• Build high-accuracy 3D full-wave electromagnetic models (HFSS) for micro-bumps, C4 bumps, TSVs, interposers, and BGA transitions, establishing automated flows for statistical eye/BER margin analysis.
• Define high-frequency test vehicles, fixtures, and measurement methodologies; execute multi-port VNA, TDR, and real-time scope characterizations to correlate lab measurements with predictive simulations.
• Collaborate closely with Silicon Design, Package Layout, Board/System, and external foundry/OSAT partners to resolve design trade-offs

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in Signal Integrity (SI), Power Integrity (PI), or high-speed hardware packaging.
• Experience in electrical channel modeling, jitter budgeting, and return loss/crosstalk optimization for high-speed serial or parallel interfaces (e.g., PCIe Gen5/6, SerDes PAM4, DDR5, or Die-to-Die interconnects).
• Experience with lab measurement equipment, including multi-port Vector Network Analyzers (VNA), Time-Domain Reflectometry (TDR), and high-bandwidth real-time oscilloscopes for simulation correlation.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience leading SI/PI technical architecture for server-class CPUs, high-performance AI accelerators (TPUs/GPUs), or multi-chiplet modules (MCM).
• Experience developing automated EM extraction, layout parsing, and high-throughput statistical eye/BER margin analysis pipelines using Python, MATLAB, or Tcl.
• Ability to lead cross-functional technical teams, mentor engineers, and drive technical roadmaps with external OSATs, substrate manufacturers, and foundries.

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in Signal Integrity (SI), Power Integrity (PI), or high-speed hardware packaging.
• Experience in electrical channel modeling, jitter budgeting, and return loss/crosstalk optimization for high-speed serial or parallel interfaces (e.g., PCIe Gen5/6, SerDes PAM4, DDR5, or Die-to-Die interconnects).
• Experience with lab measurement equipment, including multi-port Vector Network Analyzers (VNA), Time-Domain Reflectometry (TDR), and high-bandwidth real-time oscilloscopes for simulation correlation.