Capgemini

Global consulting, technology services, outsourcing

Senior Semiconductor Engineer - Multiple Teams

Hardware Validation & TestingUpdated on Nov 12

Full-timeNo salary listedIn-person

About the Job

Requirements

Sound fundamentals in SystemVerilog and experience in constrained-random and coverage-driven verification using UVM or OVM.
Experience creating UVC components or sequences is required.
Basic knowledge of at least two of AHB/AXI, PCIe/CXL, USB, DDR, serial protocols, or processor verification; expertise in one protocol is required for senior and above.
Comfort updating existing verification environments for feature updates; bringing up or architecting a UVM-based testbench from scratch is a strong plus.
Knowledge of Perl, Tcl, or Python scripting.
For senior and above, domain expertise in at least one of CPU processor/server, multimedia, automotive, Ethernet, or mobile.
At least eight years of VLSI design experience for the RTL role.
A BSc or MSc in Electrical or Computer Engineering for the RTL role.
Strong Verilog, SystemVerilog, or VHDL skills.
Experience defining microarchitecture and designing complex design units.
SoC design experience.
Proficiency in advanced design practices including lint, clock-domain crossing checks, and low-power design.
Proficiency with synthesis and static timing analysis backend tools.
Familiarity with ARM, RISC-V, or x86 CPU instruction sets.
Proficiency in Perl, C, or Python scripting and programming.
Understanding of verification methodologies.
For the physical design role, eight or more years of challenging RTL-to-GDSII work on 10 nm or below nodes with designs of 500,000 to over one million instances is desirable.
Power-user proficiency with Synopsys and/or Cadence place-and-route and timing-analysis CAD tools.
Knowledge of synthesis flow, DFT scan insertion and coverage, and optimization.
Floorplanning, power planning, clock-tree synthesis, placement, routing, and timing-closure skills.
Proficiency in Perl, Tcl, Python, and Makefile scripting.
Expertise in static timing analysis and PrimeTime signal-integrity closure, and ECO generation and implementation.
Skills in electromigration/IR-drop, DRC, LVS, and ERC analysis and fixing.
Experience with sign-off tape-out closure work.
At least six years of hands-on DFT and test-flow experience using commercial EDA tools for large and complex SoCs.
Fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500, and MBIST/LBIST.
Experience with one of Synopsys DFT Compiler, Tetramax, VCS, Tessent, or the Modus/Encounter tool suite.
Hands-on Perl, Tcl, or Python scripting.
Strong analytical and problem-solving skills.

Responsibilities

Own verification of IPs and SoCs in prototype and SoC design environments.
Establish functional and performance benchmarks.
Lead definition, execution, and continuous improvement of design-verification methodology and tool flows across verification platforms.
Perform IP and SoC design verification from RTL level through emulation.
For the RTL role, conduct feasibility studies to define system architecture, requirements, and external interfaces.
Develop microarchitecture and logic design with functional leads, delivering designs from architecture through tape-out.
Perform RTL coding, lint checks, clock-domain crossing tests, and creation of timing-constraint files.
Work with synthesis, static timing analysis, physical design, and DFT teams to meet functional, performance, power, and area goals.
Develop flows and tools to support design activities.
For the physical design role, handle full-chip or block-level physical design for advanced technology nodes of 10 nm and below.
Perform floorplanning, partitioning and budgeting, power-mesh distribution, clock-tree planning and analysis, scan reordering, placement, clock-tree synthesis, place-and-route.
Complete timing-analysis activities through sign-off, including signal-integrity/noise closure and functional and timing ECO tasks.
Perform validation and qualification activities, including formal verification, electromigration/IR-drop, DRC, LVS, antenna, and ERC analysis and fixes.
Contribute to low-power solution development and implementation.
Develop and enhance timing scripts for clock-skew and critical-path analysis, I/O interfaces, and constraint partitioning and budgeting from top level to block level.
Complete multiple complex design cycles with little supervision.
For the DFT role, implement DFT in line with existing test methodology for advanced process nodes.
Perform top- or block-level DFT insertion, including scan compression, JTAG, ATPG, pattern validation and simulation, and MBIST/LBIST.
Work with the physical design team to resolve timing constraints and issues.
Verify DFT circuitry and interfaces with other components and IPs, and debug timing-simulation issues.
Debug and improve DFT KPIs such as test coverage and pattern efficiency.
Perform hierarchical retargeting.
Support silicon bring-up, diagnosis, and physical failure analysis.

Desired Qualifications

Bringing up or architecting a UVM-based testbench from scratch.
For physical design, eight or more years of challenging RTL-to-GDSII work on 10 nm or below nodes with designs of 500,000 to over one million instances.
Top-level floorplanning, pin assignment, or tape-out activities.
Experience with RTL simulation, synthesis, linting, clock-domain crossing and reset-domain crossing checks, static timing analysis, DFT, and quality metrics.

About Capgemini:

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Your role:

DV role:

Own verification of IP’s and SoC’s in prototype and SoC design environment
Establish functional and performance benchmarks
Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms
IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

Your profile:

Sound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM
Experience in creating any UVC components or sequences is must
Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.
Should be comfortable in updating the existing verification environment for feature updates. (bring-up/Architect UVM based Test bench from Scratch is a strong plus)
EDA simulation/debugging tools agnostic
Good knowledge of Perl/TCL/Python scripting
Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.

RTL role:

Own feasibility studies for defining the system architecture, requirements, and external interfaces
Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out
Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files
Work closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals
Develop flows and tools as necessary in support of design activities.

Your profile:

8+ year experience in VLSI design
BSC/MSC in Electrical/Computer engineering
Strong Verilog/System Verilog or VHDL skills
Experience in defining microarchitecture and design of complex design units
SoC design experience
Proficient in advanced design practices (Lint, CDC, and Low Power Design)
Proficient with the various backend tools (synthesis and STA)
Familiar with CPU (ARM, RISC-V, or x86) instruction set
Proficiency using Perl/C/Python scripting and programming
Verification methodologies understanding
Good communication and interpersonal skills.

PD role:

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)
In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route
Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)
In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes
Be part of the overall Low Power solution development and implementation
Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level)
Complete multiple design cycles of high complexity with little supervision.

Your profile:

8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designs
Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence
Good knowledge of synthesis flow, insertDFT scan/coverage and optimization
Excellent floorplan, power plan, CTS, place, route, and timing closure skills
Proficiency using Perl/TCL/Python scripting and Makefile
Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill
Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills
Experience with sign-off tape-out closure work
Any top level – floor planning, pin assignment – tape out activities is a plus.

DFT role:

DfT implementation inline with existing test methodology for advance process nodes
Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST
Closely work with physical design team to resolve timing constraints/issues
Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues
Debug and improve important DfT KPIs: test coverage/pattern efficiency
Hierarchical retargeting
Silicon bring-up, diagnosis and support for physical failure analysis.

Your profile:

6+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs
Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST
Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite
Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus
Hands-on in Perl/Tcl/Python scripting
Excellent analytical, and problem-solving skills.

What Will You Love About Working Here:

Collaborative and Inclusive Culture: You’ll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.
Flexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;
Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.

Capgemini Romania is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.

About CAPGEMINI:

Capgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end-to-end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market-leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries

About the Company

Capgemini

Global consulting, technology services, outsourcing

Capgemini provides consulting, technology services, and outsourcing to help organizations transform digitally. Its offerings include strategy and transformation consulting, system integration, application development, IT infrastructure management, and managed IT operations. It differentiates itself with a global presence in over 50 countries and a focus on applying AI, cloud, and cybersecurity to real business problems. Its goal is to help clients navigate digital transformation and improve efficiency and innovation through tailored, contract-based or managed services.

Company size: 10,001+
Company stage: IPO
Headquarters: Paris, France
Founded: 1967

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