Summary

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! In the CAD organization, you will get to create new software and technologies that will enable other Apple engineers create products for millions of customers across the world.

Minimum Qualifications

Experience scripting in Python, Perl, Kotlin or TCL
Experience in Software Development with Test in-mind
Experience in Verilog and System Verilog
Minimum requirement of BS and 10+ years of relevant industry experience

Preferred Qualifications

Ability to develop solutions end-to-end
Expertise in Jasper or VC Formal products is highly desirable
Experience in formal verification is a plus
Prior customer support experience is a plus
Experience with DevOps flows is a plus
Comfortable with co-developing an existing system
Understanding of the tool flows from RTL generators, simulation and formal verification tools is a plus

Description

Formal Verification CAD engineering plays a major role in promoting a reliable work environment for Formal Verification teams. There are many applications within the formal verification arena that need support and development, such as formal property checking, low power, connectivity checks, sequential equivalence checking (SEC), and coverage. As member of our CAD team, you will develop, maintain, and enhance the flows that our internal teams use to create the next generation of Apple products. In addition to maintaining and enhancing our Formal Verification flow, the position offers a large variety of opportunities ranging from detailed application profiling and tuning to development of Continuous Integration/Deployment pipelines to large scale compute cluster management. You will have the opportunity to integrate your ideas and add new features to the system as well as collaborate with other CAD teams in various functional front-end areas. Core Responsibilities - You will be responsible for developing, maintaining, and enhancing an existing system of executing a formal verification tool - You will help out with supporting our existing Jasper reset analysis, SEC and formal proofing flows - You will utilize your debugging experience to debug vendor tool problems and interact with designers/formal verification team to help solve their problems

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

CAD Engineer

Formal Verification

Apple

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