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Celero Communications

Coherent DSP chips powering AI interconnects

Post-Silicon Validation Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-time$100k - $200k /yr

About the Job

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent experience in lieu of formal education.
  • Hands-on post-silicon validation, DVT, or silicon bring-up experience with complex ASICs or SoCs.
  • Understanding of silicon debug methodologies and structured root-cause analysis.
  • Knowledge of one or more high-speed protocols, including PCIe, Ethernet, SerDes, CXL, USB, SPI, I²C, or similar interfaces.
  • Python programming skills for automation, regression development, and data analysis.
  • Ability to work effectively across cross-functional teams.
  • Ability to work onsite full-time at the Irvine, California or Ottawa, Canada headquarters; relocation is available for qualified candidates.
  • Ability to interpret schematics and understand board design, power sequencing, signal integrity, and hardware debug.

Responsibilities

  • Perform post-silicon validation and characterization of complex ASICs and SoCs from first silicon through production release.
  • Participate in functionality, performance, interoperability, compliance, stress testing, corner-case, and reliability functions.
  • Enable first-silicon bring-up using JTAG, scan, embedded debug features, and board-level diagnostics.
  • Validate high-speed interfaces, including PCIe, Ethernet, SerDes, and other industry-standard protocols.
  • Use advanced lab equipment, including high-bandwidth oscilloscopes, BERTs, protocol analyzers, Ethernet traffic generators, network analyzers, logic analyzers, and power measurement equipment.
  • Debug complex hardware, firmware, RTL, and system-level issues with cross-functional engineering teams to identify root causes and drive resolution.
  • Contribute to Python-based automation frameworks for test execution, regression, silicon characterization, data analysis, and reporting.
  • Validate firmware, bootloaders, device drivers, and hardware/software interfaces across multiple platforms.
  • Characterize silicon performance, power, thermal behavior, margins, and compliance against architectural specifications.
  • Participate in debug reviews and provide technical direction for validation methodology, infrastructure, and best practices.
  • Support early customer engagements by reproducing and resolving system-level issues and collaborating with applications engineering.
  • Document validation results, silicon characterization data, debug findings, and production-readiness reports.

Desired Qualifications

  • Experience bringing first silicon to production in networking, communications, data center, AI, or high-performance computing products.
  • Experience using laboratory equipment, including oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, and related validation tools.
  • Experience validating firmware, embedded software, drivers, and hardware/software interfaces.
  • Experience validating coherent optical DSPs, networking ASICs, Ethernet switch silicon, AI accelerators, GPUs, storage controllers, or high-speed communications devices.
  • Strong knowledge of Ethernet, PCIe, OIF, IEEE, or related compliance specifications.
  • Experience building scalable validation automation, regression systems, dashboards, and data pipelines.
  • Familiarity with customer platform validation and hyperscale qualification processes.

About the Company

Celero Communications

Coherent DSP chips powering AI interconnects

Celero Communications designs chips that boost data center connectivity for AI workloads by using coherent DSPs to translate light signals from fiber into electrical data that computers can use. The chips embed algorithms to process optical signals over existing fiber networks, enabling high-bandwidth, long-distance data transfers between AI infrastructure clusters with lower power use. It differentiates itself by focusing on coherent DSP-based optical interconnects for large-scale AI data centers, combining deep analog and digital design expertise from industry veterans and global design centers. Its goal is to make fiber connections faster and more energy-efficient for massive AI deployments, reducing costs as cloud AI accelerators scale up.

Company size
51-200
Company stage
Series C
Total funding
$415M
Headquarters
Irvine, CA
Founded
2024

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