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Rambus

Licenses high-speed chip-to-chip connectivity IP

Principal Design Engineer

Silicon & ASIC DesignPosted on Nov 5
Full-timeHillsboro, OR, USA

About the Job

Requirements

  • RTL coding experience with Verilog and SystemVerilog.
  • A Master's degree or PhD in Electrical Engineering, Computer Engineering, or equivalent.
  • At least 8 years of experience with RTL design.
  • Good English skills.
  • Willingness to work with an international team.

Responsibilities

  • Contribute to the architecture and micro-architecture of next-generation PCIe IP.
  • Implement designs in SystemVerilog.
  • Collaborate with the verification team to verify the IPs.
  • Participate in prototyping the IPs on FPGAs.
  • Contribute to supporting existing generations of the IPs.

Desired Qualifications

  • Knowledge of PCIe or CXL.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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