Analog Bits

Mixed-signal IP for power management

Senior Mask Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timePrague, CzechiaNo salary listed

About the Job

Requirements

A diploma in Layout Design or a degree in Electrical or Electronic Engineering is required.
At least 5 years of hands-on layout design experience is required.
Experience designing layouts for high-speed phase-locked loops in advanced FinFET processes is required.
Experience using layout design and verification tools is required.
Experience in floor planning, power grid design, signal routing, and repeaters is required.
A good understanding of clock routing and shielding is required.
A good understanding of analog and mixed-signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay, and self-heating is required.
Ability to learn and ramp up on new tools and methodologies is required.
Ability to estimate realistic schedules, track progress, and report clear status is required.
Ability to work closely with the circuit design team is required.

Responsibilities

Design layouts for advanced analog and mixed-signal macros in deep submicron FinFET technologies.
Plan and implement block and top-level floor planning, power distribution networks, clock and signal routing, and analog and mixed-signal transistor-level layouts.
Use design rule checking, layout versus schematic, and other physical verification tools.
Participate in post-layout circuit performance analysis.
Estimate and track schedules.

About Analog Bits, Inc.

Analog Bits is the leader in mixed signal IP at leading edge process nodes. We specialize in developing advanced mixed signal circuits for low power, high-speed, Fin-FET mixed-signal and analog IPs that are used in numerous products from high performance data center SoCs to low power consumer SoCs.

The company is known for its trusted track record and globally respected team and goes beyond off-the-shelf offerings with flexible, tailor-made solutions. The team goes beyond best-in-class IP and superior service.

About the role

Join our European Design Center in Prague, Czech Republic and work on cutting-edge CMOS technologies including FinFETs and GAA. We are one of the very few companies in Europe actively designing with these advanced nodes—powering next-generation SoCs for data centers, AI, automotive and low-power IOT and edge AI devices.
Based in Prague — one of Europe’s most safe, beautiful and livable cities—you’ll enjoy the unique opportunity to grow your career in a vibrant cultural hub while contributing to world-class semiconductor innovation. Our Prague center plays a pivotal role in developing high-impact mixed-signal IP for global customers.

What you'll do

Layout design of advanced analog and mixed signal macros in deep Sub-Micron Fin-FET technologies.
Tasks include planning and implementing block and top-level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
DRC, LVS and other physical verification tools.
Participate in post-layout circuit performance analysis.
Estimate and track schedules.

Qualifications

Education/Certifications:

Diploma in Layout Design or a degree in Electrical/Electronic Engineering

Work Experience:

At least 5 years of hands-on layout design experience
Experience in layout of high-speed PLLs in advanced Fin-FET process
Experience using layout design and verification tools
Experience in floor planning, power grid design, signal routing and repeaters

Work Habits, Skills, and Knowledge:

Good understanding of clock routing and shielding
Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
Ability to learn and ramp on new tools and methodologies
Ability to estimate realistic schedule, track and report clear progress and status
Excellent team player and ability to work closely with the circuit design team

About the Company

Analog Bits

Mixed-signal IP for power management

Analog Bits provides mixed-signal IP (intellectual property) for intelligent energy and power management used in semiconductor chips. Its products include precision clocking macros (PLLs, oscillators), sensors to monitor temperature and voltage, and power-control blocks (like LDOs), plus integrated or separate bandgap and ADC IP. A key feature is the patented pinless/core-powered IP, which lets IP blocks be placed anywhere on a chip without external power pins while preserving analog performance, enabling easier, more reliable integration into SoCs across major foundries. The company has a 30+ year track record with silicon-proven IP across processes from 0.35 micron to 2nm and a broad portfolio designed to improve performance, cost, and reliability in applications ranging from consumer electronics and edge AI to automotive and aerospace. Its goal is to provide differentiated, easy-to-integrate IP that reduces risk and accelerates power and energy management in modern chips.

Company size: 11-50
Company stage: Not listed
Total funding: Not listed
Headquarters: Sunnyvale, CA
Founded: 1995

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