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SiMa.ai

No-code edge ML platform with MLSoC

MTS Physical Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

  • Bachelor of Engineering, Bachelor of Technology, Master of Engineering, or Master of Technology, with 12 or more years of experience in physical design using 7 nm or lower technology.
  • DDR physical design expertise is required; expertise with 3DIC or PCIe high-speed interfaces is also beneficial.
  • Timing signoff experience with Synopsys or industry-standard tools.
  • Power delivery network IR signoff and physical verification knowledge.
  • Automation skills in Python, Perl, and Tcl.
  • Proficiency in automation to drive improvements in power, performance, and area.
  • Experience working on multiple technology nodes in advanced processes.
  • Design-level knowledge to optimize implementation for power, performance, and area.

Responsibilities

  • Perform hands-on physical design of blocks from synthesis to GDS and handle complex block and/or subsystem implementation.
  • Handle physical design aspects as needed, including bump planning and coordination with SoC floorplanning.
  • Own the design of multiple blocks as a technical lead when needed.
  • Optimize power, performance, and area.
  • Develop and validate high-performance and/or low-power clock network guidelines.
  • Perform block-level place and route and close the design to meet timing, area, and power constraints.
  • Drive logic equivalency from RTL to synthesis and from synthesis to APR netlist.
  • Generate and implement engineering change orders to fix timing, noise, and electromigration/IR violations.
  • Run block-level physical design verification flows and provide guidelines to other designers for fixing LVS/DRC violations.
  • Participate in establishing place-and-route flows and physical design methodologies for correct-by-construction designs.
  • Assist in developing and refining RTL-to-GDSII flows.
  • Partner with static timing analysis teams to refine clock distribution networks and evaluate power-optimized clock gating and clock implementation strategies.
  • Architect and extend infrastructure using Tcl, Python, and Perl scripts to streamline physical design metrics reporting, automate regression suites, and explore AI/ML-driven closure techniques.
  • Serve as the central point of contact for physical design convergence, aligning RTL, DFT, and STA workflows while providing technical mentorship to team members.
  • Write Tcl, Perl, and Python scripts to improve productivity through automation.

Desired Qualifications

  • Expertise with 3DIC or PCIe high-speed interfaces.

About the Company

SiMa.ai

No-code edge ML platform with MLSoC

SiMa.ai provides a no-code, drag-and-drop environment for building, training, and deploying machine learning models on edge devices. Its platform lets users visually assemble ML solutions without writing code, and runs on its own MLSoC silicon designed for edge computing to reduce latency and speed up inference close to data sources. The product works by combining the no-code development tools with specialized edge-ready hardware, enabling deployment of ML applications such as computer vision on edge devices. SiMa.ai differentiates itself from competitors by pairing a purpose-built MLSoC with an integrated no-code development platform, plus an ecosystem of a developer portal, expert consulting, and a partner program to accelerate AI innovations at the edge. The company aims to broaden access to edge ML, helping individuals and organizations deploy efficient AI at the edge across various industries.

Company size
201-500
Company stage
Series C
Total funding
$495M
Headquarters
San Jose, CA
Founded
2018

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