Debug and Trace Architect

Salary Range: 250000 to 300000 (Currency: USD) (Pay period: per-year-salary)

Core Responsibilities

Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis.

Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities.

Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources.

Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records.

Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure the effect of tracing on workloads.

Architect performance-monitoring units and counters that expose stalls, latency, contention, and other behavior needed by software and silicon teams.

Define post-mortem capture and crash-dump requirements, including what remains accessible after a subsystem fault or host-link reset.

Establish authenticated debug-unlock levels with the Security Architect so production debug cannot expose protected data or secrets.

Set validation criteria for run control, counters, trace records, decoders, and performance tools; coordinate firmware control, silicon bring-up, and software export formats.

Minimum Education and Experience

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

At least 12 years of experience in SoC or ASIC architecture, design, verification, or silicon validation, including at least 3 years defining or leading debug, trace, performance-monitoring, or silicon-observability features.

Experience taking a debug or observability feature from specification through design and verification to silicon bring-up or production use.

Working knowledge of run control, JTAG, trace capture, performance counters, and the hardware and software interfaces needed to collect and interpret debug data.

Experience writing technical specifications and resolving implementation tradeoffs with RTL, verification, firmware, software, and silicon validation teams.

Preferred Experience

Experience synchronizing trace across multiple dies or subsystems, including timestamp alignment and cross-triggering.

Familiarity with high-bandwidth trace collection, memory-backed capture, PCIe export, or tools that convert hardware traces into software-readable formats.

Ability to drive the microarchitecture of trace funnels, counters, capture buffers, triggers, and related debug logic.

Eligibility

In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Visa sponsorship is available for this role for qualified candidates.