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Rambus

Licenses high-speed chip-to-chip connectivity IP

Design and Verification Engineer

Hardware Validation & TestingPosted on Nov 5
Full-timeSofia, Bulgaria

About the Job

Requirements

  • A Bachelor’s or Master’s degree in Electronics Engineering, Computer Science, or a related discipline.
  • At least 6 years of verification experience with Verilog and SystemVerilog.
  • At least 6 years of experience with complex ASIC/VLSI verification.
  • At least 6 years of experience with Avery or UVM.
  • At least 6 years of experience in a multinational company.
  • Experience creating documentation and using Python and shell.
  • Very good English is important for the position.
  • Open to traveling abroad.

Responsibilities

  • Perform Verilog RTL design to integrate different IPs, such as PCIe IP with a vendor PHY module.
  • Verify IP integration using a dedicated simulation environment.
  • Develop and support test cases for different verification environments.
  • Support worldwide customers with IP integration.
  • Become familiar with the existing verification process and propose improvements.
  • Maintain traceability from customer or product specifications to architecture and verification results.
  • Track and maintain verification productivity metrics.
  • Report periodically on progress and difficulties.

Desired Qualifications

  • Experience with any third-party VIP.
  • PCIe experience.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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