RTL Design Senior to Principal Engineer

Job Description and Requirements

Alternate Job Titles

• Digital Design Senior Staff Engineer
• ASIC Design Sr Staff Engineer
• RTL Sr Staff Engineer
• Senior Staff Digital IP Designer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building RTL that actually ships, not just passes simulation. The kind of RTL that holds up under post-silicon scrutiny when customers are integrating your IP into their SoC and every timing path matters. You know that a well-written micro-architecture spec is not documentation for the sake of it, it is the contract between what the protocol demands and what your design delivers.

You are comfortable sitting with a protocol standard document, extracting what matters, and translating it into clean, synthesizable design. When a verification engineer flags a corner case, you do not just patch the RTL, you trace it back to the architecture decision and fix it properly. You have debugged enough SDF-backannotated gate-level simulations to know that the real work starts after RTL freeze.

Working across borders does not faze you. You have collaborated with verification teams in different time zones, supported customer integrations where the stakes are high, and handled post-silicon bring-up calls where every cycle counts. You write code that others can read six months later, and you care about the difference between a design that works in simulation and one that works in silicon.

What You'll Be Doing

• Design and develop high-speed mixed-signal PHY IP blocks in SystemVerilog and Verilog as part of a cross-functional digital design team
• Author detailed micro-architecture specifications based on industry protocol standards, translating requirements into implementable design decisions
• Execute RTL design from concept through tape-out, ensuring design quality through Linting, CDC checks, and adherence to coding standards
• Collaborate with verification engineers to debug and resolve issues in RTL simulations and gate-level simulations with SDF timing annotation
• Provide technical support to customers during SoC integration, post-silicon bring-up, and field deployment
• Participate in design reviews and mentor junior engineers on RTL best practices

The Impact You Will Have

• Your RTL designs will power high-speed connectivity IP used in customer SoCs across automotive, mobile, and data center applications
• The micro-architecture decisions you make today will determine whether customer integrations succeed on schedule or require costly respins
• Your collaboration with verification will reduce bug escape rates and improve IP quality metrics that directly affect Synopsys revenue
• The technical support you provide will keep customer programs on track, preventing delays that could cost millions in lost market opportunity
• Your design quality and documentation will enable faster reuse across product lines, reducing time-to-market for future IP releases
• The methodologies you build will improve team productivity and reduce manual effort in future tape-outs

What You'll Need

• 5+ years of hands-on experience in ASIC RTL design flow, from specification through tape-out
• Strong proficiency in SystemVerilog and Verilog for complex digital design
• Experience with scripting languages such as Python, Perl, or Tcl for design automation
• Solid understanding of design quality checks including Linting, CDC analysis, and synthesis constraints
• Strong English communication skills for cross-functional collaboration and customer interaction
• Experience with post-silicon debugging and customer support is a strong plus
• Knowledge of high-speed serial protocols, DFT techniques, or UVM verification methodologies is a plus

Who You Are

• You can explain a complex timing closure issue to a customer engineer in two sentences without losing the technical nuance
• When verification flags an issue late on Friday, you dig in to understand root cause rather than applying a quick fix
• You write RTL comments and specs assuming the next person reading them will be you in six months
• You push back when a protocol requirement is ambiguous or a design decision will create downstream problems, and you do it constructively
• You are organized enough to manage multiple IP blocks at different stages while keeping quality high across all of them

The Team You'll Be Part Of

You will join the Digital Design team within Synopsys IP Group, working on high-speed mixed-signal PHY IP development. The team operates across Ha Noi, Da Nang, and Ho Chi Minh City, collaborating closely with verification, analog design, and customer support teams globally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.