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MatX

Designs high-throughput AI hardware chips

Emulation Engineer

Hardware Validation & TestingPosted on Nov 11
Full-timeIsraelHybrid

About the Job

Requirements

  • Strong hands-on experience with SoC emulation or system-level validation.
  • Experience with at least one commercial emulation platform, such as Palladium.
  • Working Verilog/SystemVerilog and waveform-debug skills sufficient to develop a custom transactor or agent when needed; deep RTL design expertise is not required.
  • Strong software and automation skills, including Python and one or more of C, C++, Rust, Tcl, or shell.
  • Demonstrated ability to build tools and infrastructure rather than only run existing flows.
  • Strong system-level debug instincts spanning RTL, firmware, and software.
  • Ability to work independently and across functional and team boundaries.

Responsibilities

  • Define and execute emulation strategy and test plans for complex connectivity SoCs.
  • Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu, or Veloce.
  • Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and memory models for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI, and build custom transactors where needed.
  • Develop hardware/software co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests.
  • Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows, including developing new transactors and agents from scratch when off-the-shelf options do not fit.
  • Drive emulation speed-ups and resource utilization through compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management.
  • Build automation for regression triage, debug, model usability, and engineering productivity.
  • Build practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation, including custom skills, agents, rules, and workflows suited to the engineering stack.
  • Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.

Desired Qualifications

  • UVM or hybrid SoC testbench development.
  • Integrating cycle-accurate, software, or reference models into emulation/DV flows.
  • Rust in verification or emulation flows, or strong interest in adopting it.
  • Bazel or large-scale build/regression systems.
  • Reusable stimulus across simulation, emulation, and post-silicon.
  • Using AI/LLMs to build real engineering tools for debug, triage, and flow generation beyond chat prompting.
  • Experience with connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics.
  • Firmware or driver bring-up on emulation platforms.
  • Scaling emulation or verification infrastructure across multiple projects or product lines.

About the Company

MatX

Designs high-throughput AI hardware chips

MatX builds high-throughput AI accelerators for large language models. Its main product is a dedicated chip where every transistor is optimized for running large neural networks, aiming to deliver strong performance for training and inference of LLMs. The company also develops the surrounding software stack, including compilers, to make the hardware easy to program for ML engineers (e.g., through JAX-based workflows). Unlike general-purpose processors, MatX focuses on specialization and full-stack optimization from silicon to software. Its goal is to enable organizations with substantial AI workloads to scale efficiently by providing powerful, purpose-built hardware and the compatible software tools they need to deploy and optimize large models.

Company size
51-200
Company stage
Series B
Total funding
$604.9M
Headquarters
Mountain View, CA
Founded
2022

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