Principal Engineer

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Job Description:

Candidate will join the Systems Validation Group to drive the system level validation of interfaces and architecture features for the FPGA.

Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting.

Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results

FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results.

Understand hardware architectures, use models and system level design implementations required to utilize the silicon features.

Be an effective contributor in a cross-functional team-oriented environment.

Write high quality code in Verilog, VHDL and C code for embedded processors.  Maintain existing code.

Learn new system designs and validation methodologies.  Understand FPGA architectures.

Use of on-chip debug tools.

Requirements/Qualifications:

·Excellent verbal and written communication skills in English

·Design with RTL coding in Verilog and VHDL and Verification of RTL

·Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios

·Optimizing code for FPGA architectures

·Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools

·Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE

·Working knowledge on embedded software C/C++ is also a plus

·Strong technical background in FPGA prototype emulation, and debug

·Strong technical background in silicon validation, failure analysis and debug

·Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal

·Design with RTL coding in Verilog and VHDL is a must

·Experience using Simulation (ModelSim/Questasim) and Synthesis (Synplicity) tools

Expertise in one of the areas mentioned below:

Memory Interfaces

Hands-on systems level design, debug and validation of following protocols:

• DDR4/LPDDR4/DDR5/LPDDR5 memories

Knowledge and working experience of DDR training algorithm

Experience with DDR memory controllers

knowledge of sideband I2C and I3C protocols

Ethernet

Working experience with high speed ethernet protocol upto 100GE
Skills in Network Encryption algorithms like MACsec, IPSec
Encryption algorithms AES-GCM/GMAC

BTech or MTech degree with 9+ yrs of relevant experience

Travel Time:

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