Full-Time

Technical Program Manager

Posted on 8/21/2026

Powerlattice

Powerlattice

11-50 employees

Integrated power-delivery chiplet for compute

Compensation Overview

$130k - $150k/yr

+ Stock option grant

Chandler, AZ, USA + 1 more

More locations: Vancouver, WA, USA

Hybrid

Hybrid role requires three days on-site weekly in Vancouver, WA; remote flexibility may be considered for exceptional candidates in Chandler, AZ.

Bachelor's

Category
Engineering Management (1)
Business & Strategy (1)
Required Skills
Supply Chain Management
JIRA
Risk Management
Confluence

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Requirements
  • A bachelor's degree in Engineering, Computer Science, or a related technical field.
  • At least 8 years of program management experience in semiconductor, application-specific integrated circuit/system-on-chip, or hardware product development environments.
  • Strong understanding of silicon integrated circuit development flows, including architecture, design, verification, physical design, tape-out, bring-up, and production.
  • Experience managing hardware development programs, including printed circuit board and system development and validation activities.
  • Proven experience coordinating and driving execution with third-party vendors, design houses, manufacturing partners, and suppliers.
  • Strong project planning and schedule management skills, including the ability to manage complex cross-functional dependencies.
  • Experience managing aggressive development schedules and multiple concurrent deliverables.
  • Strong risk management, problem-solving, and decision-making skills.
  • Experience using program management and collaboration tools such as Jira, Confluence, Smartsheet, Microsoft Project, or equivalent.
Responsibilities
  • Manage end-to-end engineering programs for silicon integrated circuit and hardware development projects from planning through production release.
  • Drive cross-functional execution across application-specific integrated circuit/system-on-chip design, verification, physical design, firmware, hardware, validation, operations, and manufacturing teams.
  • Develop and maintain program schedules, milestones, dependencies, resource plans, and risk assessments.
  • Coordinate with third-party vendors, design partners, contractors, and manufacturing suppliers to ensure deliverables meet schedule, quality, and cost targets.
  • Track critical-path items and proactively identify and resolve program risks, bottlenecks, and execution gaps.
  • Drive alignment between engineering teams and external partners on priorities, schedules, deliverables, and issue resolution.
  • Perform regular program reviews, status meetings, and executive updates.
  • Manage silicon development milestones, including specification freeze, register-transfer-level release, tape-out, package development, board bring-up, validation, and production readiness.
  • Coordinate hardware development activities, including printed circuit board design, prototype builds, laboratory validation, and system integration.
  • Support engineering change management, issue tracking, and escalation management processes.
  • Ensure effective communication and coordination across geographically distributed teams and external vendors.
  • Drive continuous improvement in program management processes, execution methodologies, and operational efficiency.
Desired Qualifications
  • Experience managing mixed-signal system-on-chip or high-performance silicon development programs.
  • Familiarity with semiconductor manufacturing, packaging, testing, and supply chain operations.
  • Experience supporting silicon bring-up, validation, and production ramp activities.

PowerLattice designs power delivery chiplets that attach to the processor package and regulate voltage directly at the compute die. The monolithic chiplet combines on-die magnetic inductors, voltage control circuits, vertical packaging, and a programmable software layer on a single silicon die, bringing power delivery closer to the cores. This approach reduces total compute power by over 50% and can double performance while easing cooling, and it is scalable for AI accelerators, GPUs, and data-center processors. The company sells these chiplets to hyperscalers, OEMs, and system integrators, with early trials planned for 2026, aiming to improve energy efficiency and compute performance through near-die, integrated power regulation.

Company Size

11-50

Company Stage

Series A

Total Funding

$25M

Headquarters

Camas, Washington

Founded

2023

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Simplify Jobs

Simplify's Take

What believers are saying

  • PowerLattice raised $31 million by November 2025, funding early silicon and customer sampling.
  • Management said first chiplets were manufactured by TSMC, with trials planned for early 2026.
  • AI power constraints are severe; PowerLattice claims over 50% compute-power reduction and doubled rack performance.

What critics are saying

  • Analog Devices bought Empower for $1.5 billion on May 19, 2026, crowding this niche.
  • PowerLattice still depends on TSMC samples and undisclosed trials; no production sockets exist.
  • If hyperscalers standardize on packaged IVR from ADI, PowerLattice becomes an acquisition target or dies.

What makes Powerlattice unique

  • PowerLattice embeds voltage regulation inside the package, unlike board-level power delivery.
  • Its monolithic chiplet combines on-die magnetics, control circuits, and software programmability.
  • Pat Gelsinger joined the board after the November 2025 stealth exit, legitimizing the architecture.

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Benefits

Health Insurance

Dental Insurance

Vision Insurance

Stock Options

Hybrid Work Options

Growth & Insights and Company News

Headcount

6 month growth

0%

1 year growth

-16%

2 year growth

-23%
Business Wire
Nov 18th, 2025
PowerLattice Raises $25 Million to Break the AI Power Wall

PowerLattice raised $25M led by Playground Global and Celesta. The company’s chiplet cuts compute power needs by >50%, breaking the "AI power wall."