Physical Design Engineer - Physical Verification

Team Introduction The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip. Responsibilities 1. Own and drive Physical Verification (PV) signoff for advanced-node ASIC/SoC designs, including DRC/LVS/ERC/ANT, fill program, ESD PERC/Reliability checks, GDS scramble, and advanced package related verification. 2. Own the complete PV flow from early PDK test/enablement through final tapeout, including PV methodology development, flow bring-up, debugging, and signoff closure. 3. Drive early PDK and rule-deck bring-up and validation. For immature or early-release PDKs/verification decks: analyze PV results, identify root cause (design/PDK/rule deck/technology file/tool), develop focused test cases, and work with Foundry and EDA vendors to drive closure. 4. Perform in-depth PV result analysis and debugging, including hierarchical/flat run monitoring, IP verification and SoC-level integration, regression analysis across rule-deck/PDK versions, and PV-PR correlation. 5. Act as the technical interface between the company and Foundry/PDK teams/EDA vendors, including issue reporting and tracking, test case preparation, rule interpretation discussion, and rule-deck fix validation. 6. Develop and maintain PV signoff methodology, including checklists, run strategies, waiver methodology, regression methodology, and signoff criteria. Minimum Qualifications 1. BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. 2. 5+ years of experience in physical verification (DRC/LVS/ERC) for ASIC/SoC designs. 3. Hands-on experience with industry-standard PV tools (e.g., Mentor Calibre, Synopsys IC Validator). 4. Experience with PV signoff flow from PDK enablement through tapeout. 5. Experience working with Foundry and EDA vendors on rule-deck bring-up and issue resolution. Preferred Qualifications 1. Experience with 7nm/5nm/3nm/2nm or other advanced nodes. 2. Experience with early PDK bring-up and immature rule-deck validation. 3. Experience with advanced package related PV verification. 4. Experience developing PV methodology, including waiver and regression frameworks.