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Eridu AI

AI-native networking chips for large clusters

ASIC Validation Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeSaratoga, CA, USANo salary listedIn-person

About the Job

Requirements

  • A B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • Experience in post-silicon validation and bring-up of complex ASICs or SoCs.
  • Hands-on experience with UCIe, PCIe, and high-speed interconnect standards.
  • Proficiency in Python for scripting, automation, and data analysis.
  • Lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG-based debuggers.
  • Experience working in cross-functional silicon development teams.

Responsibilities

  • Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs.
  • Own validation planning, coverage definition, and test execution across UCIe, SerDes, and networking subsystems.
  • Develop automation and test infrastructure for high-speed link and protocol validation using Python.
  • Perform silicon bring-up, including power sequencing, link training, and PHY initialization.
  • Execute link-level and system-level validation of UCIe interfaces, die-to-die interconnects, and high-bandwidth chiplet fabrics.
  • Debug complex cross-domain issues spanning RTL, firmware, analog PHY, and package-level interactions.
  • Characterize signal integrity, latency, throughput, and thermal and power behavior across PVT corners.
  • Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards.
  • Collaborate across architecture, design, firmware, and system teams to ensure first-silicon success and product readiness.

Desired Qualifications

  • Experience with chiplet-based systems, UCIe protocol stack validation, and multi-die integration challenges involving power delivery, timing, and thermal behavior.
  • Familiarity with emulation or FPGA prototyping platforms for pre-silicon validation.
  • Exposure to hardware/software co-validation for networking protocols or control-plane software.
  • Knowledge of package-level interactions and signal integrity analysis for high-speed interfaces.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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