Field Applications Engineer

TCAD-Aware SPICE model extraction with Utmost IV: from manufacturing to surrogate circuit modeling. Abstract. Accurate compact models are essential for translating device behavior into trustworthy circuit simulation, but extracting a high-quality model card can require substantial expertise, repeated optimization, and extensive manual intervention. In this webinar, Silvaco Group will introduce a new Utmost IV model-extraction flow designed to make this process faster, more efficient, and easier to manage. At the center of the flow is an improved optimizer that significantly reduces the level of user intervention required to extract a model card from device-characteristic data. Attendees will see how Utmost IV supports the progression from device data through parameter extraction, optimization, model validation, and compact SPICE model generation. The webinar will also highlight the role of Utmost IV within Silvaco's broader simulation environment, connecting device characterization and compact modeling with downstream circuit simulation. Through practical examples, Silvaco Group will demonstrate how the streamlined workflow can help modeling engineers reduce repetitive setup and optimization effort while maintaining control over extraction objectives and results. Silvaco Group will also show how Utmost IV can be incorporated into Silvaco FTCO(TM) workflows. What You Will Learn * How the new Utmost IV flow streamlines compact-model extraction from device-characteristic data * How the improved optimizer reduces manual intervention when extracting model cards * How to progress from parameter extraction and optimization to model validation and compact SPICE model generation Presenter. Sean Kelly Engineering Manager, Silvaco Sean Kelly is the engineering manager for the Utmost IV device characterization and SPICE modeling tools. He has over 35 years experience in process and device design, device characterization, SPICE modeling and EDA software development. Who should attend: Compact-modeling engineers, device engineers, characterization engineers, TCAD engineers, PDK and model-library development engineers, and engineering management. When: October 8, 2026 Where: Online Time: 10:00 Santa Clara (Live Q&A) Time: 11:00 Paris Time: 10:00 Beijing Language: English Can't attend live? The on-demand recording will be available immediately after the webinar and emailed to all registrants. Please note: Day of registration may not allow you access to live event but you will get a link to the archive.

Silvaco and Dassault Systèmes announces collaboration to accelerate advanced semiconductor packaging. August 19, 2026 The worldwide semiconductor industry has arrived at a critical physical frontier. For many years, semiconductor manufacturers depended mainly on monolithic scaling by shrinking transistor dimensions in a single piece of silicon material in accordance with Moore's law in order to increase performance and energy efficiency. Modern semiconductor designs break down large systems to small special purpose chiplets consisting of graphics cores, AI accelerators, and high bandwidth memory (HBM), all stacked up or laid side by side using silicon interposers. Yet, designing multi-chiplet 3D architectures introduces extreme physical engineering complexity. Heterogeneous assemblies suffer from multi-physics stress points: thermal hotspots, mechanical warping, electromagnetic interference, and severe mechanical stress that can crack microscopic interconnections during manufacturing. Solving these multi-physics packaging bottlenecks and accelerating time-to-market, Electronic Design Automation (EDA) leader Silvaco Group, Inc. and 3D virtual twin pioneer Dassault Systèmes announced a strategic partnership. The collaboration connects Silvaco's semiconductor simulation capabilities directly with Dassault Systèmes' 3DEXPERIENCE platform, creating an integrated, multi-physics digital twin environment engineered to enable "first-time-right" advanced semiconductor packaging. Uniting silicon physics with 3D virtual twins. The partnership bridges a long-standing tool gap: connecting sub-micron silicon physics with macro-scale structural and thermal engineering. Rather than treating chip design and package mechanics as separate sequential workflows, the alliance integrates Silvaco's TCAD modeling with Dassault Systèmes' SIMULIA simulation suite under the 3DEXPERIENCE ecosystem. Key technical and operational pillars include: Data Interoperability for Multi-Physics Analysis: Moves stress, thermal expansion, and electrical data at the sub-micron level from Silvaco products to SIMULIA tools, which allows full system warpage and stress analysis of multi-chiplet modules. Packaging "Shift-Left" Verification: Makes it possible for packaging engineers to run thermomechanical stress analysis, warpage simulation, and heat dissipation in the floorplanning stage before any test vehicle creation. Optimized Workflow Process: Combines semiconductor designers, packaging engineers, and mechanical engineering departments under one collaborative 3DEXPERIENCE platform. Better Manufacturing Yield: Aids foundries and Outsourced Semiconductor Assembly and Test (OSAT) companies in finding mechanical failure, hot spots, and solder joint fracture before manufacturing. "Advanced packaging becomes the only way of extending performance beyond the era of Moore's law," said Dr. Babak Taheri, CEO of Silvaco. Impact on the semiconductor industry. The alliance between Silvaco and Dassault Systèmes highlights major structural developments across the Semiconductors landscape: 1. Formalizing the "Shift-Left" Multi-Physics Paradigm Historically, engineers designed silicon dies first and handed the layout to packaging teams later. In 3D chiplet architectures, this sequential workflow frequently leads to thermal or warping failures during assembly. Combining TCAD physics with 3D virtual twins establishes Co-Design Multi-Physics Verification. Package mechanics and cooling channels are simulated concurrently with transistor layout, reducing redesign iterations. 2. Accelerating Commercial Adoption of 2.5D/3D Chiplets Expensive costs and poor returns have limited the uptake of cutting-edge 3D packaging by mid-level manufacturers. The provision of comprehensive EDA to 3D simulation software helps remove technical obstacles faced by mid-level chip manufacturers, automotive silicon suppliers, and communications companies. Effects of the development on businesses operating in the sector. For fabless chip manufacturers, semiconductor foundries, and OSATs, the partnership between Silvaco-Dassault is beneficial as follows: Significantly Reducing R&D Expenses on Prototypes: Virtual twins allow for reduced prototyping of wafer fabrication and save on millions of dollars in prototype wafer fabrication through reduced tape-out iterations to perform thermomechanical stress simulations. Reducing Time to Market: Design verification will enable chip manufacturers to bring 3D AI accelerators and automotive chips to market early. Improved Foundry Cooperation: Through 3DEXPERIENCE simulation standardization, semiconductor foundries and packaging companies can exchange their accurate digital twin models without compromising their intellectual property. Conclusion. The strategic alliance formed between Silvaco and Dassault Systèmes is a critical turning point in high-end semiconductor design. With the combination of simulation of silicon physics and enterprise 3D virtual twins, the software companies have provided an actionable roadmap for the 3D chiplet era. To the semiconductor sector, this development clearly indicates that future chip success will depend on a full physical simulation platform for first-time-right silicon.