Summary

Minimum Qualifications

• Minimum of BSc in EE.
• Proficient in Verilog and/or System Verilog and scripting languages.
• Understanding and application of physical design and static timing analysis principles.

Preferred Qualifications

• Familiarity with DFT insertion;
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level;
• Experience implementing ECO’s for functionality and timing.
• Experience with physical synthesis, including logic and PPA optimisation techniques.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Experience using logic equivalence tools for RTL and Gate-level designs.
• Collaborate optimally with IP teams spanning multiple sites.

Description