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Rambus

Licenses high-speed chip-to-chip connectivity IP

Hardware Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeHillsboro, OR, USA

About the Job

Requirements

  • Strong SystemVerilog and Verilog RTL design expertise.
  • Experience with Questa, Incisive, or VCS simulators.
  • Experience with Python, Perl, or Tcl scripting.
  • Significant ASIC and/or FPGA design experience.
  • Ability to learn quickly and work independently.
  • Solid communication and project management skills.
  • At least 5 years of logic design experience.
  • A Bachelor of Science in Electrical Engineering degree.

Responsibilities

  • Perform design architecting and trade-off analysis.
  • Write and verify register-transfer level code.
  • Integrate and verify Memory Controller and PHY components.
  • Provide customer delivery and support.

Desired Qualifications

  • Experience with ASIC synthesis, timing constraints, and clock-domain crossing or reset-domain crossing.
  • Verification experience.
  • Expertise with memory technologies including HBM, GDDR, LPDDR, or DDR.
  • Experience designing with AMBA AXI or CHI.
  • Located in the Hillsboro, Oregon area.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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