DV CPU ARM

<strong>Job Requirements </strong><br><p><strong style="color: black;">Responsibilities:</strong></p><ul><li><strong>Verification Planning & Strategy:</strong></li><li class="ql-indent-1">Develop detailed verification plans based on architectural specifications and functional requirements for CPU designs.</li><li class="ql-indent-1">Define verification methodologies and strategies, including testbench architecture and coverage metrics.</li><li class="ql-indent-1">Identify critical verification scenarios and edge cases.</li><li><strong>Testbench Development:</strong></li><li class="ql-indent-1">Architect and implement highly robust and scalable verification environments using UVM (Universal Verification Methodology).</li><li class="ql-indent-1">Develop complex test sequences, constrained random tests, and directed tests to achieve comprehensive coverage.</li><li class="ql-indent-1">Create reusable verification components (e.g., UVM agents, sequencers, drivers, monitors, scoreboards).</li><li class="ql-indent-1">Develop assertions (SVA) to monitor design behavior and detect violations.</li><li><strong>Verification Execution & Debug:</strong></li><li class="ql-indent-1">Execute verification plans on simulators (e.g., Cadence Xcelium, Synopsys VCS, Mentor QuestaSim).</li><li class="ql-indent-1">Debug complex functional and performance issues, identifying root causes in RTL (Verilog) and collaborating with design teams for resolution.</li><li class="ql-indent-1">Analyze coverage data (code, functional, assertion) and drive towards verification closure.</li><li class="ql-indent-1">Develop and maintain regression suites.</li><li><strong>Collaboration & Improvement:</strong></li><li class="ql-indent-1">Work closely with RTL design engineers, architects, and software teams to understand design intent and verification requirements.</li><li class="ql-indent-1">Contribute to the continuous improvement of verification methodologies, flows, and tools.</li><li class="ql-indent-1">Participate in design and verification reviews.</li></ul><p><strong style="color: black;">Minimum Qualifications:</strong></p><ul><li>Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.</li><li>3+ years of experience in digital IC verification.</li><li>Strong proficiency in Verilog and SystemVerilog.</li><li>Extensive hands-on experience with UVM for building complex testbenches.</li><li>Solid understanding of CPU architecture concepts (e.g., pipelining, cache coherence, memory management units, instruction sets).</li><li>Experience with industry-standard simulation tools.</li><li>Proficiency in scripting languages (e.g., Python, Perl, Tcl) for automation and data analysis.</li><li>Excellent problem-solving, analytical, and debugging skills.</li><li>Strong written and verbal communication skills.</li></ul><p><strong style="color: black;">Preferred Qualifications:</strong></p><ul><li><strong>Experience with ARM CPU architecture and instruction sets (e.g., ARM Cortex-A, Cortex-R, Cortex-M series).</strong></li><li>Experience with formal verification techniques (e.g., assertion-based verification, model checking).</li><li>Familiarity with emulation and FPGA prototyping for pre-silicon validation.</li><li>Knowledge of low-power verification techniques.</li><li>Experience with coverage-driven verification (CDV) methodologies.</li><li>Prior experience with performance verification and bottleneck analysis.</li></ul><br><br>