Full-Time

Senior Foundry Integration Engineer

nEye

nEye

11-50 employees

Programmable optical switches for data centers

Compensation Overview

$170k - $220k/yr

Santa Clara, CA, USA

In Person

Category
Hardware Engineering (1)

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Requirements
  • BS, MS, or PhD in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, Chemical Engineering, or related discipline
  • 7+ years of experience working with semiconductor process development or process integration
  • 7+ years of experience collaborating with semiconductor foundries or external manufacturing partners
  • MEMS or silicon photonics manufacturing experience
  • Understanding of semiconductor fabrication process flows
  • Experience defining or supporting Design of Experiments (DOE) activities
  • Strong organizational skills with the ability to manage multiple parallel engineering activities
  • Excellent written and verbal communication skills
Responsibilities
  • Own engineering tape-ins from finalized layout through successful release to external foundry partners.
  • Coordinate cross-functional tape-in readiness across Design, Layout, MEMS Integration, and Process Engineering teams.
  • Participate in tape-in quality reviews, ensuring layouts, documentation, and process assumptions are complete before release.
  • Track engineering lots from tape-in through wafer delivery and communicate status across the organization.
  • Define, coordinate, and track engineering split lots to maximize technical learning while optimizing wafer utilization.
  • Develop and manage short-loop experiments and Design of Experiments (DOEs) to investigate process issues and accelerate development.
  • Own NPI split management, including technical definition, schedule tracking, wafer tracking, engineering data collection, and results summarization.
  • Coordinate development activities with foundry engineers to ensure engineering objectives and timelines are achieved.
  • Review process flows alongside layout prior to tape-in to identify potential manufacturability or integration risks.
  • Evaluate process assumptions, mask layers, and layout interactions before fabrication.
  • Work closely with MEMS Integration Engineers to ensure process flows support device requirements.
  • Help identify opportunities to improve process robustness before engineering wafers are fabricated.
  • Perform process flow evaluations using layout review tools such as KLayout.
  • Analyze layout layers and process interactions to identify potential fabrication issues before tape-in.
  • Support simulation of process flow alternatives to improve manufacturability and development efficiency.
  • Grow into ownership of process flow modeling and simulation capabilities as the foundry development program expands.
Desired Qualifications
  • Experience supporting tape-ins or engineering wafer programs
  • Familiarity with semiconductor layouts and mask data
  • Experience reviewing process flows for manufacturability
  • Knowledge of KLayout or similar layout visualization tools
  • Experience with process simulation or process flow modeling
  • Familiarity with commercial semiconductor foundries
  • Professional proficiency in Mandarin Chinese is a plus to support technical collaboration with overseas foundry partners

nEye Systems designs programmable photonic integrated circuits (PICs) that implement high-radix optical circuit switching on a silicon chip. Their main product is a programmable optical switch built on silicon photonics, enabling high-capacity, low-power data paths for AI, ML, and other data-intensive workloads. The system uses a PIC-based switch fabric that can be configured to route optical signals through many channels, reducing electrical power needs and easing network scaling in data centers. Compared with competitors, nEye focuses on integrating high-radix, programmable optical switching directly on silicon wafers to deliver scalable, energy-efficient networking for AI infrastructure, leveraging MEMS photonics and silicon photonics techniques. The company aims to make data center networks more power-efficient and scalable to meet rising demands from AI and ML workloads.

Company Size

11-50

Company Stage

Series C

Total Funding

$152.5M

Headquarters

Berkeley, California

Founded

2020

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Simplify Jobs

Simplify's Take

What believers are saying

  • AI data centers need cheaper, denser, and more efficient interconnects.
  • Series B funding supports development and high-volume manufacturing.
  • Production samples expected next year signal commercialization progress.

What critics are saying

  • Broadcom and NVIDIA offer mature, incumbent networking alternatives.
  • Foundry, packaging, or yield problems delay revenue and samples.
  • No publicly disclosed customers or deployments limit buyer conviction.

What makes nEye unique

  • MEMS-based silicon photonics on-chip optical circuit switching.
  • Direct optical links among thousands of GPUs and memory units.
  • Chip-scale design targets lower power and smaller footprints.

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Growth & Insights and Company News

Headcount

6 month growth

35%

1 year growth

35%

2 year growth

64%
DayDayNews
Apr 12th, 2025
nEye Systems raises $58M for photonics

nEye Systems, a silicon photonics startup based in Emeryville, California, has raised $58 million in a Series B funding round led by Alphabet's CapitalG, with participation from Microsoft's M12, Micron Technology, Nvidia, and Socratic Partners. The funding will support the development and commercialization of nEye's optical interconnect chip technology, aimed at enhancing data center efficiency for AI workloads. The company claims its technology can improve energy efficiency by 100 to 1,000 times.