Full-Time

Principal Analog Design Engineer

Neurophos

Neurophos

51-200 employees

Optical metasurface AI accelerators

Compensation Overview

$225k - $280k/yr

San Jose, CA, USA

In Person

On-site role in San Jose, California or Hsinchu, Taiwan.

Category
Hardware Engineering (1)

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Requirements
  • MS or PhD in Electrical Engineering.
  • 10+ years of professional experience in full-custom analog integrated circuit design, 5+ years of dedicated experience in either GHz-speed RF or GHz-speed broadband analog design.
  • Demonstrated expert proficiency in the Cadence tool suite, specifically Virtuoso schematic, simulation, and custom layout.
  • Deep understanding of semiconductor device physics, linearity, noise analysis, and high-frequency circuit theory.
  • Proven track record of taking high-speed analog blocks from concept to mass production (successful tape-outs).
Responsibilities
  • Design, simulate, and verify high-speed analog circuits, including but not limited to high-swing drivers, transimpedance amplifiers, ADCs, DACs, and PLLs, in deep-submicron CMOS technologies.
  • Define architecture and specifications for electronic blocks based on system-level requirements.
  • Perform full-custom schematic capture, advanced analog simulations, and complete physical layout, including DRC/LVS, of critical analog blocks using Cadence Virtuoso.
  • Ensure rigorous signal integrity and power integrity across all high-speed interconnects.
  • Conduct layout floor planning.
  • Conduct post-layout extraction and simulation to validate performance against parasitic effects.
  • Collaborate closely with the Photonics and Digital teams to optimize the electro-optic interface, maximizing performance across the combination of disciplines.
  • Collaborate with team members to prepare and conduct the bench characterization and production tests.
Desired Qualifications
  • A background in photonic transceivers or optical communication electronics.
  • Extensive design experience in TSMC latest technology nodes, such as N5P, N3P, and N2P.
  • Experience designing high-speed data converters.
  • Experience designing low-jitter clocking circuits, including PLLs.
  • Proficiency in electromagnetic simulation tools such as EMX or HFSS.
  • Experience with frequency domain simulation in Spectre RF.

Neurophos designs AI accelerator chips built with optical metasurfaces and silicon photonics to deliver high-density, energy-efficient AI computation for data centers. Its processors are designed to shrink optical components by about 8000x, increasing compute power per dollar spent and reducing both capital and operating expenditures. The product works by using optical processing techniques that handle AI inference workloads more efficiently than traditional GPUs or electronic AI accelerators, enabling faster throughput with lower power use. Neurophos differentiates itself by combining optical metasurfaces with silicon photonics to achieve higher density and energy efficiency, targeting data centers and enterprises that need scalable, cost-sensitive AI inference. The company aims to reshape the AI landscape by offering faster, denser, and more energy-efficient AI computation while lowering the total cost of ownership for data centers.

Company Size

51-200

Company Stage

Series A

Total Funding

$117.2M

Headquarters

Austin, Texas

Founded

2020

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Benefits

Health Insurance

Unlimited Paid Time Off

401(k) Company Match

Stock Options

Health Savings Account/Flexible Spending Account

Dental Insurance

Vision Insurance

Life Insurance

Growth & Insights and Company News

Headcount

6 month growth

1%

1 year growth

-3%

2 year growth

0%
North Coast Co-op
Jan 27th, 2026
Neurophos secures funding round to advance photonic AI chip

Neurophos secures funding round to advance photonic AI chip. Neurophos is a semiconductor startup based in Austin, that manufactures high powered, energy efficient photonic chips for AI inference. The company was established by Dr Patrick Bowen and Dr Andrew Traverso, who have gathered a professional team of experts with deep experience from major tech and hardware companies such NVDIA, Apple and Meta. Neurophos just secured a funding round from major investors including M12(Microsoft) to advance its photonic AI chip development. The company is addressing a major bottleneck in the AI industry. Traditional silicon based GPUs are struggling to support the demands of modern AI algorithms. To solve this Neurophos has developed a novel Optical Processing Unit (OPU). Unlike traditional chips, this chip uses light-based(photonic) computing and metamaterials to perform calculations. The company has been able to achieve massive miniaturization, they have managed to shrink optical components by 10000x, allowing them to fit over a million processing elements onto a single chip. The company has claimed that the chips have huge performance gains, their technology can provide up to 100x the performance and energy efficiency of traditional chips. Neurophos also claims that their chips are more sustainable, reducing the amount of electricity required for high level AI inference, hence reducing the carbon footprint of data centers. Neurophos also chips also boasts seamless integration, the chips are designed to be drop in replacements for existing GPUs, allowing data centers to easily upgrade their infrastructure. The new capital will be used to finalize the company's first integrated compute system, expand its software stack and open a new engineering facility in San Francisco. Investors and industry experts view this as a "physics-level" breakthrough that would be able to support modern AI models, as traditional Moore's law begins to plateau.