GlobalFoundries

Semiconductor foundry delivering specialized chips

Quantum PDK Design Enablement Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-time$88k - $154k

About the Job

Requirements

A bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field is required.
Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field is required, with minimum years aligned to the applicable career level.
Experience with Design Rule Checking and/or Layout Versus Schematic rule development, coding, debugging, or qualification is required.
Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance is required.
Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions is required.
Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies is required.
Experience with scripting or programming languages such as Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis is required.
Ability to troubleshoot complex technical problems, perform structured root-cause analysis, and translate findings into robust engineering solutions is required.
Fluency in written and verbal English is required.

Responsibilities

Develop, code, qualify, and maintain Design Rule Checking, Layout Versus Schematic, and Parasitic Extraction rule decks and associated Process Design Kit components that accurately represent semiconductor process, device, interconnect, and design requirements.
Translate process integration requirements, design rules, device definitions, and electrical models into production-quality physical verification and extraction solutions for customer and internal design flows.
Develop comprehensive regression and test methodologies to validate rule-deck correctness, coverage, performance, scalability, and compatibility across supported technology and Electronic Design Automation environments.
Analyze and debug complex Design Rule Checking, Layout Versus Schematic, and Parasitic Extraction issues, identify root causes, and work with process, modeling, design, and Electronic Design Automation teams to resolve discrepancies between process intent and design-flow implementation.
Partner with process technology, design rule, compact modeling, reliability, circuit design, layout, and Electronic Design Automation teams to ensure accurate representation of semiconductor technologies throughout the design-to-manufacturing flow.
Develop differentiated automation and artificial intelligence and machine learning-assisted methodologies for rule-deck development, automated test generation, coverage assessment, error classification, anomaly detection, debugging, and continuous verification of Process Design Kit quality.
Optimize physical verification and extraction flows for accuracy, runtime, memory usage, scalability, usability, and deployment into production design environments.
Drive Process Design Kit quality and release readiness through structured qualification, regression testing, documentation, change management, and continuous improvement based on internal and customer design feedback.
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety and Security requirements and programs.
Work and collaborate on other projects and assignments as needed.

Desired Qualifications

A master's degree or PhD in Electrical Engineering, Computer Engineering, Microelectronics, Applied Physics, Computer Science, or a related field is preferred.
Experience developing and releasing production Process Design Kit Design Rule Checking, Layout Versus Schematic, and/or Parasitic Extraction rule decks for semiconductor technologies is preferred.
Experience with physical verification environments such as Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent tools is preferred.
Experience with Parasitic Extraction technology-file development, resistance-capacitance extraction, process-corner modeling, and silicon/model correlation is preferred.
Experience developing automated regression environments, rule coverage metrics, test structures, or Process Design Kit qualification methodologies is preferred.
Experience applying artificial intelligence, machine learning, generative artificial intelligence, or data-driven techniques to semiconductor design enablement, such as automated rule coding, test-pattern generation, verification debugging, error classification, or Process Design Kit quality analysis is preferred.
Understanding of interactions among process integration, design rules, optical proximity correction/lithography, device modeling, reliability, extraction, and circuit design is preferred.
Experience collaborating directly with Electronic Design Automation vendors and internal or external design teams to develop and deploy differentiated design enablement capabilities is preferred.
Strong written and verbal communication skills are preferred.
Strong planning and organizational skills are preferred.

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role

The Design Enablement Engineer, DRC/LVS/PEX is responsible for developing, qualifying, and deploying physical verification and parasitic extraction components for semiconductor Process Design Kits (PDKs). The role translates complex process and design requirements into accurate, robust, and efficient DRC, LVS, and PEX rule decks and verification flows, while advancing automation and AI/ML-assisted methodologies to improve PDK quality, development efficiency, and customer design success.

The Design Enablement Engineer develops and deploys critical PDK components that accurately represent semiconductor manufacturing processes within customer design and verification environments. The engineer will work at the intersection of process technology, design rules, device modeling, EDA, circuit design, and physical design to create differentiated physical verification and extraction solutions that enable first-time-right product designs.

The role will have particular responsibility for Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX) rule development, validation, release, and continuous improvement. The engineer will also develop advanced automation and explore AI/ML-based approaches for rule generation, test-case creation, coverage analysis, debugging, anomaly detection, and verification-flow optimization.

Essential Responsibilities

Develop, code, qualify, and maintain DRC, LVS, and PEX rule decks and associated PDK components that accurately represent semiconductor process, device, interconnect, and design requirements.
Translate process integration requirements, design rules, device definitions, and electrical models into production-quality physical verification and extraction solutions for customer and internal design flows.
Develop comprehensive regression and test methodologies to validate rule-deck correctness, coverage, performance, scalability, and compatibility across supported technology and EDA environments.
Analyze and debug complex DRC, LVS, and PEX issues, identify root causes, and work with process, modeling, design, and EDA teams to resolve discrepancies between process intent and design-flow implementation.
Partner with process technology, design rule, compact modeling, reliability, circuit design, layout, and EDA teams to ensure accurate representation of semiconductor technologies throughout the design-to-manufacturing flow.
Develop differentiated automation and AI/ML-assisted methodologies for rule-deck development, automated test generation, coverage assessment, error classification, anomaly detection, debugging, and continuous verification of PDK quality.
Optimize physical verification and extraction flows for accuracy, runtime, memory usage, scalability, usability, and deployment into production design environments.
Drive PDK quality and release readiness through structured qualification, regression testing, documentation, change management, and continuous improvement based on internal and customer design feedback.

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Work and collaborate on other projects and/or assignments as needed.

Required Qualifications

Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Computer Science, Applied Physics, or a related technical field.
Experience: Relevant experience in semiconductor PDK development, physical verification, EDA, IC physical design, parasitic extraction, or a related field, with minimum years aligned to the applicable GF career level.
Physical Verification: Experience with DRC and/or LVS rule development, coding, debug, or qualification.
PEX: Understanding of parasitic resistance and capacitance extraction, interconnect modeling, layout-dependent effects, and their impact on circuit performance.
Semiconductor Technology: Working knowledge of CMOS process technologies, semiconductor devices, layout design rules, interconnect structures, and design-to-manufacturing interactions.
EDA: Experience with industry-standard physical verification and/or extraction environments and rule-deck development methodologies.
Programming/Automation: Experience with scripting or programming languages such as Python, Tcl, Perl, shell scripting, or equivalent for engineering automation, regression testing, and data analysis.
Analytical Skills: Demonstrated ability to troubleshoot complex technical problems, perform structured root-cause analysis, and translate findings into robust engineering solutions.
Travel: Up to 10%.
Fluency in English Language: Written and verbal.

Preferred Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering, Microelectronics, Applied Physics, Computer Science, or a related field.
Experience developing and releasing production PDK DRC, LVS, and/or PEX rule decks for semiconductor technologies.
Experience with physical verification environments such as Siemens Calibre, Synopsys IC Validator, Cadence Pegasus/PVS, or equivalent tools.
Experience with PEX technology-file development, RC extraction, process-corner modeling, and silicon/model correlation.
Experience developing automated regression environments, rule coverage metrics, test structures, or PDK qualification methodologies.
Experience applying AI/ML, generative AI, or data-driven techniques to semiconductor design enablement, such as automated rule coding, test-pattern generation, verification debug, error classification, or PDK quality analysis.
Understanding of interactions among process integration, design rules, OPC/lithography, device modeling, reliability, extraction, and circuit design.
Experience collaborating directly with EDA vendors and internal or external design teams to develop and deploy differentiated design enablement capabilities.
Strong written and verbal communication skills.
Strong planning and organizational skills.

Expected Salary Range

$88,000.00 - $154,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at [email protected] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law

About the Company

GlobalFoundries

Semiconductor foundry delivering specialized chips

GlobalFoundries is a semiconductor foundry that manufactures chips for a broad range of customers, focusing on feature-rich, reliable technologies for cars, IoT, 5G, and other high-growth markets. It operates by fabricating silicon wafers for customer designs, offering mature, specialized processes rather than chasing the most advanced nodes. This makes it different from peers that prize the latest process nodes; GlobalFoundries emphasizes diversification across a global manufacturing footprint (U.S., Europe, Singapore) and stable supply for essential applications. Its goal is to be a leading supplier of high-volume, specialty manufacturing that enables reliable chips for everyday devices and growing tech markets.

Company size: 10,001+
Company stage: IPO
Headquarters: Town of Malta, New York
Founded: 2009

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