Physical Design Engineer - Full-Chip / SoC-Level

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip. Responsibilities - Own the full chip / SoC from early physical planning through final GDS/tapeout. - Define the overall chip-level physical design strategy, including die size, utilization target, and floorplanning. - Drive block partitioning, pin/bump planning, and clock architecture design. - Establish hierarchical implementation methodology. - Drive convergence across all physical-design blocks and subsystems. Minimum Qualification(s) - BS degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. - 5+ years of experience in physical design / physical implementation. - Experience owning full chip / SoC physical implementation from planning to tapeout. - Hands-on experience with industry-standard PD tools (e.g., Synopsys ICC2, Cadence Innovus). - Experience with chip-level floorplanning, clock architecture, and hierarchical methodology. Preferred Qualification(s) - Experience with 7nm/5nm/3nm/2nm or other advanced nodes. - Experience owning full chip such as server-level CPU/GPU/NPU/networking/PCIe switch.