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Synopsys

EDA software for chip design

Applications Engineering – Sr Staff Engineer

Solution EngineeringConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listed

About the Job

Requirements

  • A Bachelor's degree in Electronics and Communication Engineering and a Master's degree in VLSI, Embedded Systems, or Communication Systems are required.
  • Strong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff, including real production design exposure.
  • Deep understanding of timing constraints using SDC, MMMC analysis frameworks, and variation-aware methodologies including OCV, AOCV, and POCV.
  • Proven ability to debug complex timing issues such as setup and hold violations, clocking problems, signal integrity effects, and variability-driven failures.
  • Proficiency in Tcl scripting for tool automation and flow development.
  • Experience with advanced node designs at 5nm and below, including the unique timing challenges and signoff requirements at those geometries.
  • Ability to engage directly with customers, understand their technical challenges, and deliver solutions that work in their environment.

Responsibilities

  • Work directly with leading semiconductor companies to resolve complex timing closure and signoff challenges on advanced node designs, often under tight tapeout schedules.
  • Debug critical timing issues including setup and hold violations, clock domain crossings, signal-integrity-induced timing failures, and variation-related signoff problems using PrimeTime.
  • Guide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows tailored to 5nm and below process nodes.
  • Collaborate with R&D and product engineering teams to reproduce customer issues, identify root causes, and drive tool enhancements or methodology improvements.
  • Develop reference flows, automation scripts in Tcl and Python, and best-practice documentation that customers can adopt and adapt to their design environments.
  • Deliver technical training sessions, workshops, and live demonstrations to customer design teams, covering PrimeTime capabilities, signoff methodologies, and advanced-node considerations.
  • Drive adoption of the latest PrimeTime technologies and signoff features by demonstrating value, building proof-of-concept flows, and supporting production deployment.
  • Enable successful tapeouts for advanced semiconductor designs by solving timing signoff challenges that could delay or block production schedules.
  • Improve customer productivity and signoff quality by delivering automation scripts and methodology improvements that reduce manual effort and catch issues earlier.
  • Influence PrimeTime product direction by channeling customer pain points, design challenges, and feature requests directly to the R&D team.
  • Build long-term technical partnerships with key accounts and serve as a trusted technical advisor on complex timing signoff issues.
  • Accelerate adoption of advanced PrimeTime features across customers by translating new capabilities into production value.
  • Reduce customer support escalations by addressing methodology gaps, training design teams, and building reusable solutions.
  • Document production-tested best practices for timing signoff at advanced nodes.
  • Lead key customers and provide technical assistance on Synopsys signoff tools for key customers in India.

Desired Qualifications

  • Python or Perl scripting experience is a strong plus.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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