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Synopsys

EDA software for chip design

Analog Design Senior Architect

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeUnited StatesIn-person

About the Job

Requirements

  • A Master’s or PhD in Electrical Engineering or a related field.
  • At least 15 years of experience in memory or die-to-die interface design.
  • Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks.
  • Strong experience with power grid design and EMIR analysis.
  • Proficiency in interposer design and implementation.
  • A solid understanding of analog principles and designs, including bandgaps, LDO regulators, current mirrors, and DLLs/PLLs.
  • Deep knowledge of signal-integrity and power integrity principles.
  • Experience with layout impact on circuit performance and reliability.
  • Ability to troubleshoot and debug memory interfaces effectively.

Responsibilities

  • Review and integrate the latest multichip and interposer technologies from various foundries into HBM PHY products.
  • Define bump maps and top-level floorplans for HBM PHY products to ensure optimal performance, power, and area.
  • Collaborate with layout teams to deliver top metal covercells optimized for performance and reliability in HBM PHY designs.
  • Work with layout and SIPI teams to design interposer geometries that maximize performance and signal integrity.
  • Mentor junior engineers and provide technical guidance across multi-site teams.
  • Elevate the performance and reliability of HBM PHY products, contributing to AI and high-performance computing systems.
  • Enable integration of multichip and interposer technologies.
  • Improve manufacturability and scalability of memory interface IPs.
  • Drive technical excellence across cross-functional teams.
  • Enhance customer satisfaction by delivering robust, high-quality solutions.
  • Support Synopsys’ reputation as an IP provider through leadership, innovation, and problem-solving.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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