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SiFive

Designs and sells RISC-V semiconductor cores

Workload / Performance Model Lead

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeIn-person

About the Job

Requirements

  • A Master of Science or PhD in Computer Science or Computer Architecture.
  • At least 10 years of direct industry experience in performance simulation tools, spanning ISA to SoC/system simulators, analytical to cycle-based models, and bare-metal environments to virtual machines.
  • At least 5 years of involvement in an engineering team delivering hardware or software products.
  • A strong foundation in computer architecture for high-performance out-of-order CPU designs.
  • A strong foundation in workload characterization to identify hardware/software performance bottlenecks.
  • A strong foundation in workload reduction techniques for efficient performance simulation and projection.
  • Competency in software engineering best practices for maintaining and refactoring very large object-oriented code bases.
  • Strong object-oriented programming skills, including encapsulation, class coherency, inheritance, and polymorphism.
  • Strong Discrete Event Simulation competency, particularly in modeling techniques and best practices.
  • Ability to independently analyze performance bottlenecks in micro-architecture and software stack.

Responsibilities

  • Identify, prepare (develop or port and set up), and analyze performance for processor and accelerator development.
  • Analyze performance bottlenecks in micro-architecture and software stack.
  • Develop innovative methods to characterize workloads on simulators, emulators, and/or hardware platforms.
  • Develop performance projection methodology for complex workloads.
  • Develop and deploy efficient tools and infrastructure for performance evaluation.
  • Guide the performance team in developing benchmarks to evaluate CPU and accelerator performance.
  • Guide the team in developing and deploying performance tools for architecture development and evaluation.

Desired Qualifications

  • Awareness of known industry micro-architectures.
  • Awareness of potential security holes.
  • Hands-on expertise with either hardware development (RTL/implementation flows, verification/validation, backend flows, or FPGA flows) or software development (C/assembly, operating systems/real-time operating systems, IDEs, or compilers/debuggers).
  • FPGA debugging, including use of an Integrated Logic Analyzer for waveform capture and debugging.
  • Familiarity with git and branching/forking methodologies.

About the Company

SiFive

Designs and sells RISC-V semiconductor cores

SiFive designs and sells RISC-V based processors and related IP for use in devices and systems. Its chips come as cores and system-on-chip designs built on the open RISC-V instruction set, enabling customers to integrate high-density, energy-efficient compute into products. Unlike competitors that rely on closed architectures, SiFive leverages openness to offer flexible, scalable, and cost-effective solutions that boost compute density. The company aims to grow the RISC-V ecosystem by delivering high-performance hardware that helps customers tackle data-heavy tasks and build smarter devices.

Company size
501-1,000
Company stage
Series G
Total funding
$772.5M
Headquarters
Santa Clara, CA
Founded
2015

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