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SiTime

Fabless MEMS timing solutions provider

Principal Analog Design Engineer

Silicon & ASIC DesignUpdated on Nov 7
Full-timeArizona, USAIn-person

About the Job

Requirements

  • A master's or PhD degree in Electrical Engineering is required.
  • At least 10 years of relevant experience in analog/mixed-signal CMOS design is required.
  • Strong knowledge of integrated circuit design, device physics, and process technology is required.
  • Experience designing Phase Locked Loops (PLLs) or related building blocks is required, including phase detectors, charge pumps, LC-Voltage Controlled Oscillators (VCOs), fractional-N synthesizers, crystal oscillators, VCXOs, temperature sensors, on-chip regulators, DACs, ADCs, and similar circuits.
  • A deep understanding of transistor behavior, circuit noise theory, and phase noise concepts is required.
  • Proficiency with the Cadence analog/mixed-signal simulation toolset is required.
  • Familiarity with analog/mixed-signal design flow, simulation methods, design rules, and post-layout verification is required.
  • Experience with analog behavioral modeling using SystemVerilog, Verilog-A, or AMS is required.
  • Hands-on experience with lab testing and characterization is required.
  • English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.

Responsibilities

  • Define, design, and develop innovative circuits for high-performance timing products.
  • Mentor, lead, and guide junior designers.
  • Collaborate effectively with remote engineering teams.
  • Support prototype testing, debugging, and lab characterization.
  • Provide technical support across the full product development cycle through production release.

Desired Qualifications

  • Collaborative, self-motivated, and positive team contribution is desired.
  • Ability to empower others and provide effective mentorship is desired.
  • Strong analytical and problem-solving skills are desired.

About the Company

SiTime

Fabless MEMS timing solutions provider

SiTime designs MEMS-based timing solutions (oscillators, network synchronizers, and jitter cleaners) as a fabless semiconductor company. MEMS resonators on silicon replace quartz to generate precise clocks and synchronize networks, with manufacturing handled by third-party foundries. The approach offers smaller size, lower power consumption, and better temperature stability, supported by scalable, design-focused development rather than in-house fabrication. Its goal is to expand MEMS timing adoption across automotive, industrial, IoT, mobile, aerospace, and telecom markets worldwide.

Company size
501-1,000
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
2005

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