Design Verification Engineer

<strong>Job Requirements </strong><br><p><strong>Job Summary</strong></p><p>We are seeking a talented and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role in ensuring the functional correctness and quality of complex IP blocks and subsystems. This role requires a deep understanding of modern verification methodologies. You will be responsible for developing sophisticated, reusable verification environments from scratch using SystemVerilog and the Universal Verification Methodology (UVM).</p><p><strong>Key Responsibilities</strong></p><ul><li>Analyze design specifications and collaborate with architects and RTL designers to develop comprehensive, coverage-driven verification plans.</li><li>Architect, develop, and maintain robust, scalable, and reusable UVM-based testbench environments.</li><li>Implement key testbench components, including UVM agents (drivers, monitors), scoreboards, and sequences.</li><li>Develop and execute a mix of constrained-random and directed test cases to thoroughly validate design functionality and hit complex corner cases.</li><li>Debug RTL and testbench failures, performing deep root cause analysis using waveforms and logs, and work with designers to resolve issues.</li><li>Define and implement functional coverage models (covergroups) and assertion-based checks (SVA) to measure the effectiveness of the verification effort.</li><li>Analyze coverage reports, identify verification gaps, and develop strategies to achieve 100% coverage closure.</li><li>Enhance and maintain regression suites and automate verification flows using scripting languages to improve efficiency.</li></ul><p><strong>Required Qualifications & Skills</strong></p><ul><li><strong>Education:</strong> Bachelor’s or Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), or a related discipline.</li><li><strong>Experience:</strong> 3+ years of direct, hands-on experience in ASIC/SoC design verification.</li><li><strong>SystemVerilog Expertise:</strong> Expert-level proficiency in SystemVerilog, including a strong grasp of Object-Oriented Programming (OOP) concepts, constrained-random stimulus generation, and assertion-based verification (SVA).</li><li><strong>UVM Mastery:</strong> Deep, practical experience with the Universal Verification Methodology (UVM). This includes building complete testbenches with agents, sequencers, scoreboards, and leveraging the UVM factory and configuration database.</li><li><strong>Verification Fundamentals:</strong> Solid understanding of modern verification principles, including coverage-driven methodologies, test planning, and advanced debug techniques.</li><li><strong>Protocol Knowledge:</strong> Hands-on experience verifying at least one standard industry protocol such as AXI, AHB, PCIe, DDR, Ethernet, or similar.</li><li><strong>Tools:</strong> Proficiency with industry-standard EDA simulation tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa.</li><li><strong>Scripting:</strong> Strong scripting skills in a language like Python, Perl, or Tcl for automation.</li></ul><p><strong>Preferred/Desired Qualifications</strong></p><ul><li>Experience with C/C++ for creating reference models or for co-simulation environments.</li><li>Familiarity with formal verification techniques and tools.</li><li>Experience with Gate-Level Simulations (GLS) and debugging timing-related issues.</li><li>Knowledge of low-power verification techniques (UPF).</li><li>Prior experience contributing to post-silicon validation and debug.</li></ul><br><br><strong>Work Experience </strong><br><p><strong>Job Summary</strong></p><p>We are seeking a talented and detail-oriented Design Verification Engineer to join our core team. As a DV Engineer, you will play a crucial role in ensuring the functional correctness and quality of complex IP blocks and subsystems. This role requires a deep understanding of modern verification methodologies. You will be responsible for developing sophisticated, reusable verification environments from scratch using SystemVerilog and the Universal Verification Methodology (UVM).</p><p><strong>Key Responsibilities</strong></p><ul><li>Analyze design specifications and collaborate with architects and RTL designers to develop comprehensive, coverage-driven verification plans.</li><li>Architect, develop, and maintain robust, scalable, and reusable UVM-based testbench environments.</li><li>Implement key testbench components, including UVM agents (drivers, monitors), scoreboards, and sequences.</li><li>Develop and execute a mix of constrained-random and directed test cases to thoroughly validate design functionality and hit complex corner cases.</li><li>Debug RTL and testbench failures, performing deep root cause analysis using waveforms and logs, and work with designers to resolve issues.</li><li>Define and implement functional coverage models (covergroups) and assertion-based checks (SVA) to measure the effectiveness of the verification effort.</li><li>Analyze coverage reports, identify verification gaps, and develop strategies to achieve 100% coverage closure.</li><li>Enhance and maintain regression suites and automate verification flows using scripting languages to improve efficiency.</li></ul><p><strong>Required Qualifications & Skills</strong></p><ul><li><strong>Education:</strong> Bachelor’s or Master’s degree in Electrical Engineering (EE), Computer Engineering (CE), or a related discipline.</li><li><strong>Experience:</strong> 3+ years of direct, hands-on experience in ASIC/SoC design verification.</li><li><strong>SystemVerilog Expertise:</strong> Expert-level proficiency in SystemVerilog, including a strong grasp of Object-Oriented Programming (OOP) concepts, constrained-random stimulus generation, and assertion-based verification (SVA).</li><li><strong>UVM Mastery:</strong> Deep, practical experience with the Universal Verification Methodology (UVM). This includes building complete testbenches with agents, sequencers, scoreboards, and leveraging the UVM factory and configuration database.</li><li><strong>Verification Fundamentals:</strong> Solid understanding of modern verification principles, including coverage-driven methodologies, test planning, and advanced debug techniques.</li><li><strong>Protocol Knowledge:</strong> Hands-on experience verifying at least one standard industry protocol such as AXI, AHB, PCIe, DDR, Ethernet, or similar.</li><li><strong>Tools:</strong> Proficiency with industry-standard EDA simulation tools like Synopsys VCS, Cadence Xcelium, or Siemens Questa.</li><li><strong>Scripting:</strong> Strong scripting skills in a language like Python, Perl, or Tcl for automation.</li></ul><p><strong>Preferred/Desired Qualifications</strong></p><ul><li>Experience with C/C++ for creating reference models or for co-simulation environments.</li><li>Familiarity with formal verification techniques and tools.</li><li>Experience with Gate-Level Simulations (GLS) and debugging timing-related issues.</li><li>Knowledge of low-power verification techniques (UPF).</li><li>Prior experience contributing to post-silicon validation and debug.</li></ul><br><br>