Power Methodology and Modelling Engineer

THE ROLE

The focus of this role is to drive SoC power efficiency methodology with a primary focus on RTL and architecture. The engineer will support the development of IP and SoC power models, analyze power-performance tradeoffs, and identify opportunities to improve power efficiency across AMD products.

THE PERSON

You have a passion for modern processor architecture, digital design, and verification. You are a collaborative team player with strong communication skills and experience working across global teams and time zones. You possess excellent analytical and problem-solving abilities, a passion for learning, and the initiative to tackle complex technical challenges.

KEY RESPONSIBILITIES

• Contribute to SoC power methodology, RTL power analysis, and optimization to improve power efficiency across the SoC.
• Collaborate with architecture, RTL design, verification, and power teams to identify, evaluate, and implement power-efficiency features and enhancements.
• Analyze power and performance tradeoffs using power models, RTL simulations, workloads, and design data to support product power targets.
• Evaluate simulation and emulation traces for power projection and correlate projections with power-model predictions and silicon data when available.
• Support the development and continuous improvement of SoC power models and methodologies, with opportunities to grow ownership of power-modeling activities.
• Analyze power results, identify key power contributors and anomalies, and work with design teams to drive RTL power optimizations.
• Drive power-efficiency ideas from concept through RTL implementation, validation, and measurable power improvements.
• Apply power methodology and analysis techniques to identify and implement RTL and SoC-level power-efficiency enhancements.

PREFERRED EXPERIENCE

• Strong foundation in RTL design, digital logic, and SoC architecture, with exposure to CPU, memory subsystems, fabrics, I/O, clocking, or power-management features.
• Experience with, or strong interest in, RTL power analysis, low-power design techniques, power methodology, and power-efficiency optimization.
• Understanding of power-management concepts and how architecture and RTL design decisions impact SoC power and performance.
• Exposure to power modeling, power projection, and model-based power analysis methodologies.
• Experience with hardware emulation and the use of emulation traces for power projection and analysis is a plus.
• Interest in learning and growing expertise in SoC power modeling, methodology development, power projection, validation, and correlation.
• Strong analytical and problem-solving skills with the ability to identify and drive power-efficiency opportunities across engineering disciplines.
• Programming and scripting experience, with Python preferred.

ACADEMIC CREDENTIALS

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

LOCATION

Santa Clara, CA

#LI-PA1

This role is not eligible for visa sponsorship.