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Voltai

AI world models for chip design & manufacturing

RTL Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timePalo Alto, CA, USANo salary listedIn-person

About the Job

Requirements

  • At least 5 years of RTL design experience on chips that have taped out.
  • Expert-level SystemVerilog and Verilog skills and strong microarchitecture skills.
  • Hands-on experience with lint, clock-domain crossing, synthesis, and timing-aware design.
  • Familiarity with common protocols such as AXI, PCIe, Ethernet, DDR, or similar.
  • Python or Tcl scripting.

Responsibilities

  • Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
  • Drive designs through lint, clock-domain crossing and reset-domain crossing, synthesis, and timing closure with the backend team.
  • Partner with verification and formal teams on test plans, assertions, and coverage closure.
  • Debug complex functional and timing issues across simulation, emulation, and silicon.
  • Review and evaluate AI-generated RTL, and help define correct, high-quality design.
  • Work directly with customer design teams when needed.

Desired Qualifications

  • Experience writing SystemVerilog Assertions or working with formal verification.
  • Low-power design experience, including UPF, clock gating, and power gating.
  • Interest in AI-assisted design tools.

About the Company

Voltai

AI world models for chip design & manufacturing

Voltai builds AI models and agents that learn, plan, and experiment in the physical world, starting with semiconductor design and manufacturing. Its world models run virtual experiments, then validate results in real fabrication settings to build rich datasets across the hardware stack. What sets Voltai apart is a team of Stanford researchers, former chip-industry CTOs, and policy veterans working with major semiconductor, electronics, and automotive manufacturers. The goal is to speed hardware innovation through AI-driven simulation and validation.

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