Design for Test Lead

<strong>Job Requirements </strong><br><ul><li><span style="color: rgb(92, 95, 102); background-color: rgb(255, 255, 255);">Hands on Technical lead with SoC & Netlist level DFT execution experience and one can guide juniors </span></li><li><strong>Scan Insertion</strong>: Stitching every flop in the design into shift registers (scan chains) to set the chip to any state and observe any state.</li><li><strong>ATPG (Automatic Test Pattern Generation)</strong>: Running tools to generate patterns that detect manufacturing defects via the scan chains.</li><li><strong>MBIST (Memory BIST)</strong>: Inserting on-chip memory test logic to allow RAMs and ROMs to self-test in the field.</li><li><strong>Boundary Scan and JTAG</strong>: Utilizing boundary scan and JTAG techniques for testing.</li><li><strong>Collaboration</strong>: Working closely with design and verification teams to optimize for test efficiency and fault isolation.</li><li><strong>Integration</strong>: Integrating test structures within the design of electronic components to facilitate efficient testing throughout the product lifecycle</li></ul><br><br>