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Eridu AI

AI-native networking chips for large clusters

RTL Engineer - Networking ASIC

Silicon & ASIC DesignUpdated on Nov 13
Full-timeSaratoga, CA, USANo salary listedIn-person

About the Job

Requirements

  • A bachelor's or master's engineering degree (ME/BE) and 8–15 years of experience are required.
  • Hands-on knowledge of SystemVerilog and Verilog is mandatory.
  • Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
  • Proven expertise in designing and optimizing scheduling and quality-of-service mechanisms.
  • Experience with Ethernet and IP protocols is required.
  • Prior experience with on-chip memory subsystems and scheduling or arbitration design is required.
  • Strong analytical and problem-solving abilities and meticulous attention to detail are required for troubleshooting and debugging complex networking issues.
  • Excellent verbal and written communication skills are required, including the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Responsibilities

  • Define, specify, architect, execute, and productize cutting-edge networking chips.
  • Work on microarchitecture and implementation of high-speed networking ASICs, focusing on latency optimization and quality-of-service support.
  • Implement designs on ASIC platforms in compliance with industry standards and performance benchmarks.
  • Work with the verification team to conduct thorough testing and validation for functionality and reliability.
  • Analyze and optimize pipelining architectures to improve performance metrics.
  • Provide support for networking protocols such as Ethernet and IP, and high-speed interconnects such as UCIe.
  • Investigate and resolve complex packet-queuing issues in collaboration with system architects, hardware engineers, and firmware developers.

About the Company

Eridu AI

AI-native networking chips for large clusters

Eridu AI designs AI-native networking chips and systems that replace multi-hop optical tiers in large GPU training clusters. Their products place more networking functions on-chip within a redesigned switch stack, which reduces power consumption, cost, and latency as GPU bandwidth scales. This approach differs from traditional Arista-like gear by integrating switching functionality directly into silicon, aiming for highly scalable, energy-efficient networking for hyperscale cloud providers, AI labs, and enterprises running million-GPU-class clusters. The company targets large-scale GPU deployments and seeks to make data-center networking more efficient, scalable, and cost-effective, backed by substantial funding from major investors to support growth and deployment.

Company size
51-200
Company stage
Series A
Total funding
$230M
Headquarters
Saratoga, CA
Founded
2024

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